Biography
Enrollment Date: 2012
Graduation Date：2015
Degree：M.S.
Defense Date：2015.06.02
Advisors：Zhihua Wang
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：
A wide tuning and low phase noise 9G~11G PLL design
Abstract:
The PLL circuit is a very important unit of modern RF communicationcircuit. It is widely used for it’s many excellent characteristics. PLL is the most critical part of the frequency synthesizer which is used to provide the local signal.The RF integrated circuit has developed to a very high altitude under 10GHz.But the design of 10Ghz RF intergrated circuit still face great challenges.This paper focuses on the research about phase locked loop circuit covering 10GHz and analyzes the difficulties and challenges of high frequency PLL.
This paper first introduces the definition,principle and characteristics of the PLL,and describes the PLL linear model.The two order, three order phase PLL open loop transfer function and its stability is analyzed.Describes several common indexes to evaluate the performance of PLL.The detailed analysis of PLL main parts and it’s principle is provided. A model of PLL noise is proposed to analysis the noise of PLL,and some methods used to reduce the noise is proposed.
A 9-12GHz complementary cross-coupling LC_VCO with a wide tuning range, 5 bits digital control and low phase noise is presented in chapter 4. The final measured results of the chip achieve a tuning range of 9.1 GHz to 11.93 GHz, a phase noise of -116.4 dB/Hz at 1 MHz offset from the carrier frequency of 10.19 GHz, a oscillation core power consumption of 13 mW at a 1.3 supply voltage and a chip area of 0.5mm2.
The working principle and design method of Pearce oscillator is discussed in the chapter 5. A high precision, high stability crystal oscillator Pearce with ±100PPm and 0.1 tuning step size is designed and fabricated in TSMC 0.18-um CMOS technology.
The other parts of PLL,including a pulse swallow divider with a 195~226 divide ratio,a divide-by-2 working above 6 Ghz,a traditional static PFD without dead zone,a singal end charge pump,and a 2 order loop filter,is designed and post simulated.Finally,a wide tuning range and low phase noise 10GHz PLL is presented.