Biography
Enrollment Date: 2012
Graduation Date：2015
Degree：M.S.
Defense Date：2015.06.02
Advisors：Zhihua Wang Dongmei Li
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：Design and Implementation of a 6-Bit 1GS/s Successive Approximation Register Analog-to-Digital Converter
Abstract:
Due to the high energy conversion efficiency and mostly digital nature, successive approximation (SAR) Analog-to-digital converter (ADC) is increasingly widely used. The power and speed performance of digital circuits have been driven by the scaling CMOS technology, thus making SAR ADC a hot topic. This dissertation presents a new capacitor array architecture to achieve a 6 bit 1.2V 1Gs/s energy-efficient SAR with 65nm CMOS.
The research of this dissertation include four parts:
1) Several topologies to achieve high speed ADC are listed, detailed analysis and comparison are made to determine proper topology for the desired specification.
2) A new capacitor array architecture is proposed for high speed SAR ADC, meanwhile, a method to correct the parasitics in the DAC array is proposed.
3) To speed up the SA logic, a bypass logic is developed, the critical path of SAR logic is well optimized.
4) Designs high speed interface circuits, including clock input and data output.
The SAR ADC is designed in TSMC 65nm 1P9M technology. The whole circuit system, layout and post simulation have been finished，and simulation results reach the desired specification. Test scheme and the PCB test circuit are well prepared. The die area of the chip is 1490um*1210um. Post layout simulation results show that the SAR achieves ENOB of 4.7 with sampling rate at 1Gs/s, input frequency at Nyquist frequency.