Biography
Enrollment Date: 2012
Graduation Date：2015
Degree：M.S.
Defense Date：2015.06.02
Advisors：Woogeun Rhee
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：Study of Nonlinearity and Delay Mismatch Calibration in Two-Point Modulator
Abstract:
Recently, the broadband mobile applications are developed rapidly, followed by the urgent requirement for low-cost and high-speed transmitters. The Polar transmitter has the advantage of low power consumption due to the lack of digital to analog converter and mixer. Besides, the Polar transmitter can use digital amplitude modulation, which is easy to control. With these advantages, the Polar transmitter becomes a good choice for multi-mode modulation transmitter design.A wide bandwidth phase modulation is necessary in Polar transmitter. The direct frequency modulation based on fractional phase-locked loop (PLL) required lower power consumption. However, the data rate is limited by PLL bandwidth. Two-point modulator can avoid the PLL bandwidth’s limitation on data rate. However, three main problems exist in this architecture: gain mismatch, delay mismatch and nonlinearity of Digital/Voltage-controlled Oscillator (D/VCO). Based on in-depth study on the non-ideal effects in two-point modulator, a multi-bit high-pass modulation path is put forward to calibrate the D/VCO nonlinearity. The compensation in the high-pass modulation path is realized. The modulation signal is processed by a multi-bit nonlinear quantizer to compensate the D/VCO nonlinearity.. The states of the thermometer capacitor banks are determined by some 8-tap FIR filters. This architecture can reduce the switch noise coupling, and enlarge the FIR filter’s bandwidth to ensure the high data rate modulation quality.Then, fine delay calibration based on divider and multiplexer is designed for delay mismatch between the two modulation paths. High-resolution clock signals are required. Utilizing current mode logic and digital divider-by-2 to build divider-by-8 can divide the D/VCO output differential signals into 16 signals with lower frequency and well-distributed phases. The time different between adjacent two phases is 138 picoseconds. The low-pass delay mismatch calibration part can be separated into two paths with different trigger clocks. Fine delay control between high-pass path and low-pass path can be realized by multiplexers.Finally, with UMC 180nm CMOS technology, a low data rate phase modulator with nonlinearity calibration is designed. In this modulator, the nonlinearity calibration method is proved. With TSMC 65nm CMOS technology, a high data rate phase modulator with both D/VCO nonlinearity calibration and delay mismatch calibration is taped out. In this chip, the delay time between high-pass modulation path and low-pass modulation path can be controlled finely. Measurement results show that the proposed nonlinearity calibration architecture and delay mismatch calibration architecture are reliable for high data rate phase modulator design.