Biography

Enrollment Date: 2012

Graduation Date：2015

Degree：M.S.

Defense Date：2015.06.02

Department：Institute of Microelectronics，Tsinghua University

Title of Dissertation/Thesis：Design of Ultra-low Power and Ultra-low Voltage Phase Locked Loop for Mobile Healthcare Applications

Abstract:
For mobile health application, steady and reliable timing is very important. With the increasing demand for the efficient and portable mobile health products, the study of ultra-low power and ultra-low supply becomes the hot issue gradually. Since PLL (Phase Locked Loop) is an indispensable building block, it is crucial that how to design the ultra-low power and ultra-low supply PLL with good noise performance, and the innovations on circuit level are desirable. In this thesis, the current techniques about low power and low supply are well studied and analyzed. Based on those research works, a 0.35V~0.5V，18MHz~152MHz newly relaxation digitally-controlled oscillator (DCO) is proposed. It can operate at as minimum as 0.35V supply with 17.8W power consumption at 26MHz output, and its phase noise is as good as －104dBc/Hz at 1MHz offset; while the supply voltage is 0.5V, it consume 59W power at 100MHz output, and its phase noise is －103.4dBc/Hz at 1MHz offset. This relaxation DCO does not suffer the start-up issue which exists in ring DCO. Also, the process variation and temperature variation are both carefully considered during this design. With the proposed relaxation DCO, a 0.55V, 100MHz, PVT-tolerant ADPLL (All-digital PLL), which is consisted of PLL circuits,  modulated LDO (Low dropout regulator) and temperature variation tolerant circuits, is proposed in this thesis. This design is released through two times tape-out in 65nm CMOS process. The testing results from the first time’s manifest: the power consumption of the circuits is 67.7W at 0.55V supply, and the phase noise at 1MHz offset is －82.9dBc/Hz. The LDO achieves well PSRR (Power supply rejection ratio) when sinusoidal noise is injected to the supply.

Publications

Papers：：

[1] Yudong Zhang,Xiaofeng Liu,Woogeun Rhee,Hanjun Jiang,Zhihua Wang, A 0.6V 50-to-145MHz PVT tolerant digital PLL with DCO-dedicated ΔΣ LDO and temperature compensation circuits in 65nm CMOS, ISCAS 2017, pp. 1 - 4, 2017.

[2] Yudong Zhang,Woogeun Rhee,Taeik Kim,Hojin Park,Zhihua Wang, A 0.35–0.5-V 18–152 MHz Digitally Controlled Relaxation Oscillator With Adaptive Threshold Calibration in 65-nm CMOS, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol.62, No.8, pp. 736 - 740, 2015.

[3] Yudong Zhang,Woogeun Rhee,Zhihua Wang,Taeik Kim,Hojin Park, A 0.55V 100MHz ADPLL with ΔΣ LDO and Relaxation DCO in 65nm CMOS, RFIT 2015, pp. 190 - 192, 2015.

[4] Yu Li,Fei Chen,Dang Liu,Xiaoyong Li,Yang Li,Yudong Zhang,Zhicheng Wang,Woogeun Rhee,Zhihua Wang, A 1.6Mb/s 3.75–4.25GHz chirp-UWB transceiver with enhanced spectral efficiency in 0.18μm CMOS, RFIT 2014, pp. 1 – 3, 2014.