Biography
Enrollment Date: 2012
Graduation Date：2015
Degree：M.S.
Defense Date：2015.06.02
Advisors：Fule Li
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：ADC IP Design for High-speed Wireless Local Area Network SOC
Abstract:
With advance in deep sub-micron CMOS process, integration level of chips becomes higher and more circuits are integrated on System-on-Chips (SOC). Analog-to-Digital Converters (ADC) are the indispensable part for system because they can convert analog signal to digital signal. Successive-Approximation-Register (SAR) ADCs consume low power and operate at high speed as the channel length of transistor shortens and supply voltage decreases because of its unique structure. Therefore, SAR ADCs apply to high-integration and low-power SOCs, such as wireless local area network SOCs.
ADC IPs used in wireless local area network need to meet the system demand for high performance and low power consumption. An 11bit 80MS/s dual-channel SAR ADC IP and an 11bit 160MS/s dual-channel SAR ADC IP are designed in this thesis. Both of them are fabricated in SMIC 55nm low leakage CMOS process. The two IPs adopt subranged SAR ADC architecture which consists of a 3.5bit front-end FLASH ADC and an 8bit back-end SAR ADC. FLASH ADC not only decreases dynamic power consumption from reference voltage, but also realizes capacitors in MSB (Most Significant Bit) are controlled by thermometer codes to obtain better Differential Non Linearity (DNL). Since there is a 0.5bit resolution redundancy in this design, ±1/32 full scale range offset or aperture error can be tolerated. There are some more key points in this work: bottom sampling is used to avoid charge injection effect on sampling network; segmented capacitor array is adopted to decrease capacitance, DAC power consumption and layout area; optimization of paracitic capacitor in DAC, bootstrap switch sampling and matching design of capacitor array ensure good linearity of ADC; dynamic comparator which consumes no static power is applied to reduce the ADC power consumption; high-speed asynchronous SAR logic based on a gate-controlled ring oscillator is proposed to improve ADC conversion speed.
Two SAR ADC chips have been taped out and tested. 11bit 80MS/s SAR ADC IP consumes 1.75mW/channel and achieves an SNDR of 60.9dB and an SFDR of 74.6dB with 2.4MHz input frequency at 100.11MS/s, and an SNDR of 57.5dB and SFDR of 66.4dB with 50MHz input frequency. 11bit 160MS/s SAR ADC IP consumes 2.45mW/channel and achieves an SNDR of 60.88dB and an SFDR of 71.57dB with 4.9MHz input frequency at 150MS/s, SNDR of 49.96dB and SFDR of 57.71dB with 70MHz input frequency. The test results show two SAR ADCs achieve system demand for high speed and low power consumption.