Biography
Enrollment Date: 2012
Graduation Date：2015
Degree：M.S.
Defense Date：2015.06.02
Advisors：Fule Li
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：12-bit 1GS/s Pipeline Analog-to-Digital Converter Design
Abstract:
Analog-to-digital converter (ADC) is a bridge connecting the real world and the digital system which has a wide range of applications. The high speed and high resolution ADC is one of the core technology in advanced applications such as communications systems, military electronics systems, high-speed measurement systems. In which, the ADC’s performance is relating to the merits of the overall system performance. Therefore, high performance ADC becomes a hot research topic in today's academic and industry.
This paper introduces the research status of high-performance ADC at home and abroad, summarizes its development trend and research significance. On this basis, this paper studied the bottlenecks in improving ADC’s performance and put forward some method to enhance the accuracy and speed, lower power consumption. In view of the proposed ideas, this paper designed a 12 bit resolution, 1GHz sampling rate high performance pipeline analog-to-digital converter.
The ADC has the following characteristics: (1) An input buffer in the front end of the structure which on the one hand can effectively reduce the driving difficulty, on the other hand can reduce the negative influence of the sample and hold circuit’s kick back noise at the sample time; (2) Using the time interleaving strategy with one channel sample/hold amplifier (SHA) and two-channel interleaving quantizer. The SHA is flip-around structure which can achieve full frequency operation in single channel and avoid complex multi-channel clock skew calibration, the stage circuits in quantizer is slower which can be realized by time interleaving to reduce single-channel switching speed, optimizing the overall system power consumption, the offset/gain mismatch calibration between dual channel is relatively simple, which can be corrected by an on-chip digital calibration circuit. (3) Implemented in a 65nm CMOS process, the analog power supply is 2.5V in order to increase the dynamic range of the signal, while using thick oxide transistor for protection, using thin oxide transistor for switches, trans-conductance and key nodes for 1GS / s conversion speed; (4) using a high-gain high bandwidth folded-telescopic operational trans-conductance amplifier (OTA); (5) The entire ADC is equipped, which includes the conversion core and peripheral circuits such as bandgap reference, on-chip high-speed reference buffer, low-jitter clock receiver, LVDS and a large number of decoupling capacitors .
Based on the proposed circuit design strategy above, this paper designed the schematic, layout and carried out the simulation.. The overall data converter area including LVDS and IO interface is 2mm×2mm, in which the core area is 1.15mm×0.8mm. At low frequency input and typical corner, pre-layout simulation shows 11.9-bit ENOB and 79.6dB SFDR at 1GS/s sampling rate. Post-layout simulation shows 11.8-bit ENOB and 80.2 dB SFDR for the ADC core.