Biography
Enrollment Date: 2012
Graduation Date：2015
Degree：M.S.
Defense Date：2015.06.03
Advisors：Hanjun Jiang
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis： A Low Power 24-bit Δ-Σ ADC for ECG Signal Acquisition
Abstract:
Wearable health monitoring system can meet people’s need of acquiring information about their health conditions and physical indexes. One of the most important applications is wearable ECG(electrocardiogram) acquisition system. Although the wearable ECG acquisition system has achieved marked progress, there is still room for growth, especially in power consumption and accurac of the analog-front-end(AFE). This thesis shows an improved structure of AFE proposed by the project team and focuses on the key circuit technologies of ADC, then proposes a 24bit ΔΣ ADC under the 0.18μm CMOS process. The paper has following achievements.
First, this paper proposes a new AFE to solve the problems in practical applications after in-depth research of the current AFE for ECG acquisition system. The area and design challenge of the Instrumentation Amplifier(IA) are reduced by using a high dynamic range ΔΣ ADC. The new AFE can also solve many kind of the practical issues such as baseline drift, effectively.
Second,this paper proposes a low-power 24bit ΔΣ ADC under the 0.18μm CMOS process. with the purpose of improving accuracy and saving power consumption, the ADC uses a 3rd order 5bit modulator structure with feed forward path. It also reduces the design difficulty of OTA. The 5bit quantizer uses a structure of Asynchronous Successive approximation with Analog adder, which reduces the complexity of the circuit.The nonlinear problems aroused by 5bit DAC are solved by using dynamic element matching module, which assures ADC’s accuracy. The detailed design process of each module is presented in paper and all the experimental results demonstrate that the ΔΣ ADC achieves 109dB SNR(Signal-Noise Ratio) and consumes 306μW total power dissipation. The FOM is competitive compared with similar kinds of ΔΣ ADC.
Third, A low-power 24-bit ΔΣ ADC designed for ECG acquisition with dynamic adjustment is presented. The ADC can achieve 120.4 dB SNR and 19.71 bit ENOB in high-speed mode; 108.4 dB SNR and 17.71 bit ENOB in low-speed mode. By adding a QRS detector with dynamic adjustment, the ADC can adjust the working mode according to the wave form of ECG. As to a typical ECG, the amount of data with dynamic adjustment can significantly reduced to 62.5% as compared to the conventional design, while the average power consumption of ADC can be reduced to 101.5 μW, 66.7% of the ADC with no dynamic adjustment.