Biography
Enrollment Date: 2011
Graduation Date：2014
Degree：M.S.
Defense Date：2014.05.27
Advisors：Liji Wu
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：Design and Implementation of Key Modules in 10Gbps Ethernet Security Processor
Abstract:
In times of Big Data and Cloud Computing, with more and more fiber-optic network access being available to customers and 40Gbps/100Gbps network devices being popular in backbone network, developing 10Gbps Ethernet Security Processor, the core chip in network security, is very important and urgent for ensuring online information security. Base on IEEE 802.3ae 10Gbps Ethernet standard, this paper designs and implements 10Gbps Ethernet Physical Coding Sublayer (10G BASE-R PCS), which is the key communication module of 10Gbps Ethernet Security Processor. A multi-stage pipelined table look-up method 64B/66B encoding module and an M-sequence self- synchronized parallel scrambling module have been proposed to achieve 10Gbps signal processing. A method of bit wide conversion between asynchronous clock domains has been proposed to achieve 10Gbps data stream 66B/32B seamless bit wide conversion. An improved quick synchronization head test method has been put forward with 76% faster synchronization speed compared with the standard one. Implemented and tested on Virtex-6 FPGA platform, the PCS proved to satisfy the functional and performance requirements. This paper designs and implements a Network Security Processor (NSP) FPGA functional verification platform, fulfilling functional test of core control unit and enabling the processor flexibility and configurability to some degree. Besides a test pattern generation method is proposed to contribute to the test of NSP chip. Based on a server main board provided by Inspur, a 10Gbps Ethernet communication testing environment, which simulates the whole communication process, has been built to testing the usability of PCS. Furthermore, a 10Gbps Ethernet Security Process prototype has been implemented, of which functional test and performance test has been done. This paper concerns with 10Gbps Ethernet Security Processor, designs and implements 10Gbps Ethernet Physical Coding Sublayer, and fulfils the integration and verification of a 10Gbps Ethernet Security Processor.