Biography
Enrollment Date: 2011
Graduation Date：2014
Degree：M.S.
Defense Date：2014.05.26
Advisors：Zhihua Wang
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：Critical techniques of PLL Applied in High Speed SerDes
Abstract:
As the requirement of data transmission rate becomes higher and higher, SerDes has been used in interface circuits widely, because of its several advantages like high speed and perfect on anti-interference. As for the different applications, PLLs for SerDes have many different issues on designing process. This thesis analyzed the characteristics of PLLs for SerDes and designed a PLL for 40 Gbps SerDes. The whole structure has been simulated and the significant part has been taped out and tested. en simulated substantially to make sure that it will work when tape it out. Unlike traditional wireless transceivers, the communication bandwidth of SerDes is from baseband to the highest clock frequency, so the PLL’s high frequency offset phase noise also added to the jitter of the System. On the contrary, PLL’s low frequency offset phase noise was ignored because of CDR. Meanwhile, the suppression of Spur and VCO’s phase noise is contradictory. All of these makes the selection of loop bandwidth in SerDes applicantion has amount of different with wireless transceivers. Subject to noise model analysis and optimum loop bandwidth calculation, a VCO with 4 bit switch-capacitors was proposed to reduce the VCO gain. An adaptive switch-capacitor controller was designed to achieve the automatic adjustment of the switch-capacitor. For suppression of the Spur and low frequency offset phase noise, a pseudo differential charge pump with dual loop feedbacks was adopted. It has many advantages, like small current mismatch, Insensitivity for capacitor leak current, suppression of clock forward back and charge injection, Insensitivity of signal delay and low noise. A frequency selection circuits and a locking detection circuits was designed to achieve the mode alternative between full and half speed and give the signal of clock ready. The loop bandwidth and the zero and poles could be set up for different reference. The VCO and Output buffer has been taped out and tested. The result is that, the tuning range is from 18.25 GHz to 22.61 GHz, the phase noise at the frequency of 18.25 GHz is -100.7 dBc/Hz. Substantial simulation has been made for the whole PLL. The stability simulation says that the phase margin of the loop is 61.18°.Simulations for VCO says that the tuning range is from 17.8 GHz ~ 22.19 GHz and the phase noise at 20 GHz is -106.4 dBc/Hz. Simulations for charge pump shows that the current mismatch is less than 5% between the voltage is from 0.25V to 0.75V. The adaptive controller worked well and could select the right frequency band for the VCO.