Biography
Enrollment Date: 2011
Graduation Date：2014
Degree：M.S.
Defense Date：2014.05.26
Advisors：Fule Li
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：The Design of Current Steering DAC IP with High Speed and High Resolution and the Application of Calibration
Abstract:
With the overall development of the IC technology in device, process and design, the data processing systems are processing larger volume of data at a higher speed, which raises higher requirements on the data interface circuits. The data interface circuits are supposed to have higher speed and accuracy. The rapid increasement in integration gives a rise to the progress of SoC technology, and as a result, data interfaces such as ADCs and DACs are often designed as an Intellectual Property module instead of standalone chips, but the requirements in area and power consumption are stricter for IP modules.Firstly, an 11bit 200MS/s 2-channel current-steering DAC IP is presented. A 6-2-3 segment scheme is used to achieve the trade-off between logical complexity and linearity. The current array is organized in a one-dimensional distribution to save the area and the wiring layer. Synchronous latch is applied to improve the dynamic performance. The 2-cascode structure is used to improve the static matching performance. It is shown in the test results that DNL≤0.25LSB and INL≤0.8LSB. SFDR is up to 72dBc at 4.88MHz input frequency. The total area of this IP is only 0.3mm2 and it has been used in a baseband transmission system.Then a 16bit 1GS/s DAC IP is presented. To meet the matching requirements, the gate area of each MSB current source is at least 2300μm2 in the conventional design method that depending on the process matching performance. Calibration is applied to improve matching performance and optimize area. The total area of an MSB current source and its calibration circuits is decreased to less than 1000μm2 with calibration. Behavioral simulation shows good matching performance with DNL≤0.45LSB and INL≤0.95LSB. Quad-switch is used to purify output spectrum. The core layout is complete and post-simulation is done. The core area is about 1240μm*390μm. It is given by post-simulation results that the SFDR is up to 83.9685dBc at 1GS/s with a 100MHz input frequency. Simulation results show good overall performance of this DAC IP.