Biography
Enrollment Date: 2011
Graduation Date：2014
Degree：M.S.
Defense Date：2014.05.26
Advisors：Fule Li
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：High-speed and High-resolution Pipelined Analog to Digital Convertor Low-power Front-end Design
Abstract:
As a signal processing circuit, data converter is an important role between analog and digital world, which is the bridge connecting to worlds. With the rapid development of communication, image processing, and radar, high performance processors requires higher performance data converter. Meanwhile, a single chip can be integrated more functional modules, which means that the power consumption of the data converter has become a major challenge. Thus, high performance and low power data converters become the hotspot of academic and industrial research.Pipelined architecture is the first choice of high speed and high resolution data converter. In the pipelined ADC, SHA and the first stage is the key of whole system. And it deciedes the chip`s resolution and consumption. This paper dedicates the related technologies study for the front stage of high-speed high-resolution pipeline data converter. Firstly, the status of academic and industrial research for high performance data converter is introduced. To deal with these non-ideal effects, exiting solutions and key technologies are studied and summarized. On this basis, this paper based on TSMC 180nm technology designed a 14 bit resolution, 250MHz sampling rate high performance pipeline data converter. And the circuit optimization and innovation for the front stage includes: (1) A new front stage timing scheme. The aperture error caused by the signal path can be effectively reduced, with dynamic comparator, without increasing the clock pulse. Since the dynamic comparator is used, the power consumption is greatly reduced. (2) According to the circuit offset, power consumption and noise, etc., the front stage is optimized for the resolution. (3) Design the adjustable gain OPAMP, depending on the characteristics of the process corners, to maintain good linearity under different conditions. (4) Design adjustable threshold voltage circuit, eliminating the comparator offset by threshold voltage compensation. Finally, the whole chip circuit design and layout is completed. This chip is supplied by 1.8V. The overall data converter area is approximate 2mm × 3mm, and the core area is 2mm × 0.7mm. At 30MHz input signal, with extracting the parasitic capacitance, simulation result shows that 12.29 bit effective resolution, 90.08dB SFDR, 75.76dB SNDR. At 118MHz input signal, 12.07 bit effective resolution, 84.77dB SFDR, and 74.44dB SNDR. Simulation results show that the circuit can meet the design requirements.Another aspect of this paper is the measure results of the 10bit 120MS/s pipeline data converter (first chip) and the 14bit 250MS/s data converter (second chip). Since the sampling rate of the first chip is lower, logic analyzer is used to measure. When the input signal is at 4.9MHz, the resolution can reach 8.9bits, SFDR of 74dB, SNDR of 55.34dB. The design of the first chip is compatible with AD9218, and the performance is better than AD9218, such that it has commercial value. The sampling rate of the second chip is higher, and LVDS+FPGA is used to measure this chip. When the input signal is at 15.5MHz, without calibration, the SNDR can reach 67.75dB and SFDR of 82.43. After calibration, the SNDR can reach 68.54dB and SFDR of 95.11dB for the second chip.