Biography
Enrollment Date: 2011
Graduation Date：2014
Degree：M.S.
Defense Date：2014.05.26
Advisors：Fule Li
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：Study on Analog-to-Digital Converter for CMOS Image Sensor
Abstract:
This thesis presents the design of a pixel level analog-to-digital converter (ADC) circuit and a chip level analog-to-digital converter (ADC) circuit for CMOS image sensors.Pixel level ADC is that each pixel in CMOS image sensor contains an ADC. Due to this fully parallel A/D conversion, very low conversion speeds can be achieved, and low power, low noise and small layout area should be. This paper introduces a variety of pixel level ADC implementations, and on this basis this pixel level ADC adopts voltage reset technique to balance the charge packet, and achieves analog-to-digital conversion through counting charge packets. Firstly, this paper describes the working principle of pixel level ADC in detail, a 50Hz 15-bit pixel level ADC is implemented with the proposed principle. This ADC is fabricated in SMIC 0.18um CMOS process with 1.8-V supply, the comparator, counter and memory are also included in the ADC chip. A single pixel level ADC has an area of 45×45μm2 and the digital part (counters and memories) occupies nearly 85% of the ADC area. The simulation results show that the ADC consumes less than 2μW with the input current of 80nA. From the measured results, when the input currents are 1nA, 40nA and 80nA, the mean values/the standard deviations of the output code are 400/0.829, 16877/0.919, and 32700/1.75 respectively.
This paper also presents the design of some circuit modules in chip level ADC, which uses pipeline structure. A 14-bit, 250Ms/s pipelined ADC is described that is implemented in SMIC 55nm CMOS process. The main research objects involved in this paper are subADC in pipeline ADC architecture, especially study on switched-capacitor comparator and the low-jitter clock receiver.