Biography
Enrollment Date: 2004
Graduation Date：2007
Degree：M.S.
Defense Date：2007.06.01
Advisors：Chun Zhang
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：Study and Hardware Implementation of Key Algorithm in H.264 Decoder
Abstract:
H.264/AVC video is the latest video codec standard and it is developed by the joint team of the ITU-I Video Coding Experts Group and the ISO/IEC Moving Picutre Experts Group. After introducing the flow of video decoding, this paper then focus on two models of IQ/IT(inverse quantization and inverse transform) and intra prediction. The close study includes two steps: algorithm analysis and hardware implementation. After analyzing the algorithm of IT(inverse transform), the paper gives a computing architecture which can deals with all 3 types inverse transform. In the hardware implementation of the architecture, there is a trade-off between speed and resource cost and then the paper gets a core architecture of inverse transform circuit including a 1D computing model and 4×4 transpose. A 4×4 matrix can be decoded in at most 9 cycles. The inverse quantization is also studied and a hardware implementation is given. The inverse quantization works when the date is loaded or stored. After combining two circuits we get a co-processor which can be used by other H.264 decoder, of course, with suitable interface. The paper also pays great attention to intra prediction. The paper gets the bottleneck of the intra prediction and gives a hardware solution to it after having a close analysis of the 3 type intra predictions. The architecture can gives one intra prediction in one cycle. Considering speed and cost, the paper gives a parallel architecture which can compute luma and chroma prediction value in the same time. With proper interface circuit, the parallel architecture can be used as a co-processor by other H.264 decoder. To match the decoder system proposed by the team, the paper gives proper interface circuit.