Biography
Enrollment Date: 2011
Graduation Date：2014
Degree：M.S.
Defense Date：2014.05.26
Advisors：Woogeun Rhee
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：Design of an All-Digital Phase Locked Loop with a ΔΣ ADDLL-based TDC
Abstract:
With the technology scaling and the tight requirement of power dissipation of integrated circuit, the design of the traditional analog phase-locked loop (PLL) becomes more challenging than ever. Since recent applications demand the PLL has good PVT robustness, programmability and reliable design migration with the advanced CMOS technology, all digital phase-locked loop (ADPLL) is now a research hotspot.
This paper first discusses the existing structures of the ADPLL, pointing out that the time-to-digital converter (TDC) is one of the most critical block for the phase noise and spur performance of the ADPLL. Operation principle and performance factors of the TDC and various architectures are studied. A delay-locked loop (DLL) based TDC is adopted in this design for its PVT robustness, good linearity, dynamically adjustable resolution and spur reduction by dithering.
Based on the behavioral simulation, the feasibility of using a ΔΣ ADDLL（all digital delay-locked loop）based TDC for the ADPLL is verified in this thesis. The ΔΣ module operates based on the dynamic change of a digital delay control word rather than choosing output phases in the delay chain, the spurs of ADPLL output spectrum can be well suppressed when the ΔΣ module is enabled. By considering the the ΔΣ ADDLL effect on the ADPLL performance, the mechanism of sudden changes of the phase error is deeply discussed, and a phase error compensation module is proposed, which can effectively eliminate the sudden phase error change.
The circuit implementation of the key modules is described in detail. An improved digital control delay line realizes approximately inverse relationship between the delay control current and the digital control word, thus achieving good improvement of the linearity and delay range. A conventional LC digitally-controlled oscillator (DCO) is designed and achieves the tuning range of 2.0-2.5 GHz.
The chip described in this paper has been taped out in 0.18m CMOS. The core area is 6.4 mm2. The ADPLL consumes 12.8 mA from a 1.8V supply, where the TDC consumes 2.7 mA. Testing results show that the ΔΣ ADDLL TDC based ADPLL works properly, achieving the spur suppression of nearly 15dB when the ΔΣ modulator is enabled. In this work, the feasibility and the effectiveness of the proposed ΔΣ ADDLL TDC based ADPLL is verified in hardware, which can provide references for subsequent researches.