Biography
Enrollment Date: 2011
Graduation Date：2014
Degree：M.S.
Defense Date：2014.05.29
Advisors：Woogeun Rhee
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：Low-cost Delta-Sigma Frequency-Locked Loop Design with High Frequency Accuracy
Abstract:
Production cost and power consumption reduction are two main objectives of today’s active research related to the communication filed. And frequency locked loops have some advantages, such as wide locking range and easily digitizing, are extensive applied as auxiliary module, its limitation is the accuracy of FLL.This paper will introduce a new FLL structure, which achieves highly digital design and high-precision low-cost, to meet the future applications demands.
This design uses 1-bit frequency detector (FD), which not only achieves a high precision FLL in GHz band, but also avoids high precision TDC of ADPLL that requires advanced technology.
This paper will firstly elaborate on an all-digital FLL(ADFLL), including module design, loop structure, circuit implements, and its prototype is fabricated in 0.18um CMOS, the simulation results and testing results will shows in the paper. It could be applied in the wireless communication, such as FM-UWB.
Furthermore, on the basis of this ADFLL, the paperproposed an improved version, which uses a PLL to realize the constant gain DCO. For the deficiencies of this ADFLL, the new FLL proposes several improvements to improve noise characteristics and frequency accuracy, and it can be applied in the spread spectrum application, comply with the requirements of SATA and other wireline communication applications.