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Yun Yin

Biography

Enrollment Date: 2010

Graduation Date：2015

Degree：Ph.D.

Defense Date：2015.06.06

Advisors：Baoyong Chi

Department：Institute of Microelectronics，Tsinghua University

Title of Dissertation/Thesis：Research on Key Techniques of Software-Defined Radio Transmitter RF Chip

Abstract:
With the rapid development of wireless communication, traditional radio frequency (RF) transceiver chips have limited flexibility and boost the cost for multi- band multi-standard applications. Software-Defined Radio (SDR) technique provides the cost-efficient solution for multi-mode multi-band wireless communication. With the goal of high integration, low power and high performance, the key techniques of SDR transmitter RF chip are researched in this dissertation. This dissertation proposes novel reconfigurable design techniques on frequency band, signal bandwidth, power consumption and system architecture, which are suitable for most SDR transmitters design, and is successfully verified with a dual-path reconfigurable transmitter front-end. This dissertation proposes a linear/non-linear reconfigurable CMOS power amplifier (PA). The PA has switchable Class-AB and Class-F operation modes, which meets the high efficiency and high linearity requirements of constant-envelope and non-constant-envelope modulation schemes, respectively. The measured results show that the PA achieves above 19dBm output P1dB (OP1dB) and above 20% power-added efficiency (PAE) over 0.1-1.5GHz in the Class-AB mode; in the Class-F mode, the maximum saturation output power of 23.2dBm with the peak PAE of 60% has been achieved. This dissertation proposes a high output power, PAPR-tolerant dual-mode PA, based on the transistor-stacking and load modulation techniques. Besides, a power- control loop is introduced to detect the input signal PAPR and dynamically reconfigure the operation mode to enhance the back-off efficiency. The measured results show that the PA in the high power mode (HPM) achieves 27dBm OP1dB and 26.1% PAE; in the low power mode (LPM), the OP1dB of 22dBm with the PAE of 21.8% is obtained. By utilizing the LPM, the PAE of HPM-only PA is improved by ×2 (21.8% LPM versus 10.9% HPM) at 5dB back-off power. In this dissertation, the self-calibration techniques for the SDR transmitters are discussed, including RF resonant frequency self-tuning, LO leakage and image self- calibration as well as output power detection. Benefited from the digital calibration techniques and algorithms, complete self-calibration techniques are utilized in the SDR transmitter design to enable a more practical chip. Based on the above techniques, two SDR transmitter chips are implemented in 65nm CMOS. The first transmitter chip is highly-integrated, including JESD207 interface, digital signal processing, frequency synthesizer and CMOS PA, and supports 0.1-5.0GHz multi-standard applications. In the second transmitter chip, FSK and BPSK modulators are further integrated on-chip. Besides, its power dissipation is reduced by adopting the current-mode up-conversion architecture and the complete self-calibration scheme is implemented.

Publications

Papers：：

[1] Yun Yin,Baoyong Chi,Zhigang Sun,Xinwang Zhang,Zhihua Wang, A 0.1-6.0-GHz dual-path SDR transmitter supporting intraband carrier aggregation in 65-nm CMOS, IEEE Transactions on Very Large Scale Integration Systems, Vol.23, No.5, pp. 944 - 957, 2015.

[2] Yun Yin,Xiaobao Yu,Zhihua Wang,Baoyong Chi, An efficiency-enhanced stacked 2.4-GHz CMOS power amplifier with mode switching scheme for WLAN applications, IEEE Transactions on Microwave Theory and Techniques, Vol.63, No.2, pp. 672 - 682, 2015.

[3] Xiaobao Yu,Meng Wei,Yun Yin,Ying Song,Siyang Han,Qiongbing Liu,Zongming Jin,Xiliang Liu,Zhihua Wang, Yichuang Sun, Baoyong Chi, A Fully-Integrated Reconfigurable Dual-Band Transceiver for Short Range Wireless Communications in 180 nm CMOS, IEEE Journal of Solid-State Circuits, Vol.50, No.11, pp. 2572 - 2590, 2015.

[4] Xiaobao Yu,Meng Wei,Yun Yin,Baoyong Chi,Zhihua Wang, A Sub-GHz low-power transceiver with PAPR-tolerant power amplifier for 802.11ah applications, RFIC 2015, pp. 231 - 234, 2015.

[5] Yun Yin,Yanqiang Gao,Zhihua Wang,Baoyong Chi, A 0.1–5.0GHz self-calibrated SDR transmitter with −62.6dBc CIM3 in 65nm CMOS, CICC 2015, pp. 1 - 4, 2015.

[6] Bing Lyu,Yun Yin,Xiaobao Yu,Baoyong Chi, A 0.1-1.5G SDR Transmitter with Two-Stage Harmonic Rejection Power Mixer in 65-nm CMOS, ASICON 2015, pp. 1 - 4, 2015.

[7] Yun Yin,Baoyong Chi,Zhaokang Xia,Zhihua Wang, A Reconfigurable Dual-Mode CMOS Power Amplifier With Integrated T/R Switch for 0.1–1.5-GHz Multistandard Applications, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol.61, No.7, pp. 471 - 475, 2014.

[8] Yun Yin,Baoyong Chi,Yanqiang Gao,Xiaodong Liu,Zhihua Wang, A 0.1–5.0 GHz Reconfigurable Transmitter With Dual-Mode Power Amplifier and Digitally-Assisted Self-Calibration for Private Network Communications, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol.61, No.11, pp. 3266 - 3277, 2014.

[9] Yun Yin,Baoyong Chi,Zhihua Wang, Efficiency-enhanced self-biased PA driver for multi-standard applications, Electronics Letters, Vol.50, No.13, pp. 927 - 928, 2014.

[10] Yanqiang Gao,Yun Yin,Wen Jia,Baoyong Chi, A Reconfigurable Digital Intermediate Frequency Module for Software Defined Radio Transmitters, ICSICT 2014, pp. 1 - 3, 2014.

[11] Yun Yin,Baoyong Chi,Xiaobao Yu,Wen Jia,Zhihua Wang, An Efficiency-Enhanced 2.4GHz Stacked CMOS Power Amplifier with Mode Switching Scheme for WLAN Applications, CICC 2014, pp. 1 - 4, 2014.

[12] Xiaobao Yu,Meng Wei,Yun Yin,Ying Song,Siyang Han,Qiongbing Liu,Zongming Jin,Xiliang Liu,Zhihua Wang, Baoyong Chi, A fully-integrated reconfigurable dual-band transceiver for short range wireless communication in 180nm CMOS, A-SSCC 2014, pp. 257 - 260, 2014.

[13] Xinwang Zhang,Baoyong Chi,Meng Cao,Ling Fu,Zhaokang Xia,Yun Yin,Hongxing Feng,Xing Zhang,Patrick Chiang, Zhihua Wang, A 0.1–4 GHz SDR receiver with reconfigurable 10–100 MHz signal bandwidth in 65 nm CMOS, Analog Integrated Circuits and Signal Processing, Vol.77, No.3, pp. 567 - 582, 2013.

[14] Yun Yin,Baoyong Chi,Zhihua Wang, A 0.1–1.5GHz dual-mode Class-AB/Class-F power amplifier in 65nm CMOS, MWSCAS 2013, pp. 372 - 375, 2013.

[15] Yun Yin,Baoyong Chi,Qian Yu,Bingqiao Liu,Zhihua Wang, A 0.1-5GHz SDR transmitter with dual-mode power amplifier and digitally-assisted I/Q imbalance calibration in 65nm CMOS, A-SSCC 2013, pp. 205 - 208, 2013.

[16] Xinwang Zhang,Yun Yin,Meng Cao,Zhigang Sun,Ling Fu,Zhaokang Xia,Hongxing Feng,Xing Zhang,Baoyong Chi, Ming Xu, Zhihua Wang, A 0.1∼4GHz receiver and 0.1∼6GHz transmitter with reconfigurable 10∼100MHz signal bandwidth in 65nm CMOS, CICC 2012, pp. 1 - 4, 2012.