Biography
Enrollment Date: 2004
Graduation Date：2006
Degree：M.S.
Defense Date：2006.12.28
Advisors：Yongming Li
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：Design of High Resolution Pipelined A/D Converter
Abstract:
The analog-to-digital converter is one of the most important modules, in the design of high integrated and high speed SOC. In the application of video signal process and digital communication, The A/D converter should have high conversion rate (above 10M SPs) and high accuracy (ENOB larger than 10 bits). The pipelined A/D converter is largely used because it offers the best trade of among speed, accuracy, area and power. But the relative accuracy is still a challenge in design of pipelined ADC. In this thesis, all kinds of error sources due to non-ideality are analyzed in the way they affect the sub stage output voltage, and corresponding remove methods are proposed. A simple capacitor select technique is propose, which reduces the requirement of capacitor matching with very simple circuits. A high accuracy pipelined A/D converter IP is designed, reformative passive capacitor mismatch error-averaging technique is employed, which reduces the capacitor match requirement to 1/27. Input SHA is abrogated for low noise and low power. Folded cascade and gain boosting are employed in the design of operational amplifier (OPA). Its dc gain is 120dB, and its bias current can vary from 10uA to 100uA. In the first two stages, clock boosted NMOS is employed on their input analog path, which improve the linearity effectively. Simulation of the ADC with package model included is performed; the result shows that the SFDR is 89.5 dBc，SNDR is 77.9 dB and the ENOB is 12.65 bit. In the layout design, isolation between digital and analog circuit is carefully considered. Key cells are designed with good matching and isolation, and small load. The source and sub of digital transistors are connected to different power ring. Digital and analog circuit are separated by a wide ground path, and a mass of decoupling MOS and finger capacitor is placed. The impact of bonding wire is considered, and the corresponding AC model is constructed to estimate the minimum amount of decoupling capacitor, which can effectively decouple the digital pulse interference. Area of the whole ADC including decoupling capacitor, PAD and cell ring is not larger than 1.6×1.8mm2, and has been fabricated with SMIC 0.18 µm Mix-signal process.