Biography
Enrollment Date: 2010
Graduation Date：2014
Degree：M.S.
Defense Date：2013.12.17
Advisors：Chun Zhang
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：Research and Design for Transmitter Circuit of 10Gbps/14Gbps High Speed SerDes
Abstract:
With the advent of big data time, people have got more and more urgent demands on the communication with a high data transfer rate. Serial communication has replaced parallel communication and become a main way of data transmission. High-speed SerDes is the core part of serial communication. It has been widely used in such areas as high-performance processor interconnection and optical communication, etc. In addition, various interface standards have been made. To take Infiniband Architecture for example, single-channel transmission rate is constantly developing towards higher transmission rate according to the route of 5Gbps-10Gbps-14Gbps. Therefore, it is of great significance to research and design high-speed serial integrated transceiver at a velocity of 10Gbps and above.
Based on the 10Gbps high-speed SerDes transmitter designed with SMIC 65nm CMOS LL technique, this paper makes a in-depth analysis and study on circuit configuration and function. It carries out a comprehensive PVT simulation of all circuit modules. According to the simulation result, the bottleneck and key point for speeding up the circuit is found; the potential problems existing in the design are discovered and solutions are presented; after simulating the complete transmitter in the testing system model with channel load, it’s verified that the chips of the transmitter basically can formally work at 10Gbps.
For the circuit modules which restrict the transmitter from being speeded up, this paper improves circuit structure specifically, thereby to increase the operating speed of the circuit. Use CML Logic Multiplexer to replace the original Digital Multiplexer; use Continuous Time Linear Equalizer to replace the original Feed-forward Equalizer. Clock buffer link is optimized. A testing system model, with packaging and Printed Circuit Board trace, etc. included, is set up. Finally, the design and simulation of the 14Gbps high-speed SerDes transmitter is completed. The improved transmitter has got a correct function and stable performance. The comparison between the new transmiter at 14Gbps and the original transmitter at 10Gbps is shown below: At the same time when the speed is improved, the power consumption isn’t increased obviously. After running through the same length PCB transmission line, the signal swing received by the new transmitter is increased by 55%, jitter is reduced by 85%, and all other parameters meet the design specifications.