Biography
Enrollment Date: 2010
Graduation Date：2014
Degree：M.S.
Defense Date：2014.05.27
Advisors：Hanjun Jiang
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：Research and Design of a 12-Bit Successive Approximation Register Analog-to-Digital Converter
Abstract:
The continued development of theory, technology and process of integrated circuit has caused the trend of greater integration levels and large-scale system on a single-chip. At the same time, low-power and high-speed design are focused on widely. Successive-approximation register analog-to-digital converter (SAR ADC) is widely used in industrial control and armamentariums, because of its excellent performance in accuracy, area and power efficiency.
This paper discusses the SAR ADC principle and the difficulties in designing a 12-bit 660KS/s SAR ADC with a 1.8V power supply.
The main content contains 4 points: 1.The principle of SAR ADC, the circuit structure of the ADC, and the qualification of it. 2.Decide the circuit structure of the DAC module and have a further research on the calculation of capacitance, analysis of gain error, offset and calibrator. 3.Have a further research on the comparator module and the digital control logic. 4.Finish designing the circuit and test the result.
This paper finished a 12 bit 660KS/s SAR ADC based on the UMC 180nm 1P6M process. A two split three components capacitive DAC (CDAC) is designed to optimizing the sampling capacitance area and power efficiency. A three stages low noise offset-calibrating comparator is also designed. Test results shows that 11.1 ENOB and 86dB SFDR can be achieved by using this design method without calibration.