Biography
Enrollment Date: 2010
Graduation Date：2013
Degree：M.S.
Defense Date：2013.05.29
Advisors：Dongmei Li
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：Research and Design of a 16-Bit Successive Approximation Register Analog-to-Digital Converter
Abstract:
Successive approximation register analog-to-digital converter (SAR ADC) is used to achieve the conversion of an analog signal to a digital one. Compared to other analog-to-digital converters, SAR ADC occupies a wide range of market because of its advantage of moderate accuracy, moderate speed and relatively low power consumption. It has been widely employed in electronic areas such as industial and medical field. This thesis studies the key techniques and design difficulties of a 16-Bit SAR ADC, which works under 1.8V supply voltage and 1MHz sampling frequency. This paper maily introduces four parts: ①The working principle of SAR ADC is systematically explained, as well as the typical structure and the performance indicators. ②Charge-redistribution structure in full-differential input mode and a calibration method aimed at decreasing the effect of capacitor mismatch are adopted. ③The design and realization of the main modules (sampling switch, digital-to-analog converter, comparator, control logic and calibration circuits) are presented in details. ④Improvements are proposed on the basis of the chip`s measurement results. This paper proposes a 16-Bit SAR ADC fabricated in UMC 180nm CMOS process. The bootstrapped sampling switch is used to reduce the nonlinearity. Split capacitive digital-to-analog converter is adopted, and the comparator with multi-stage structure achieves a compromise between precision and power consumption. A single loop 1st-order 4-bit quantizer is used in the delta-sigma type circuit, wherein the CDS and Chopping techniques eliminate the flicker noise and relax the performance requirements on OTA. The nonlinearity caused by the multi-bit quantization is weakened by DEM technique based on DWA algorithm. The chip occupies an area of 1.3mm*1.2mm. The measurement results show that at 1MHz sampling rate, the 16-Bit SAR ADC can achieve 70.8dB peak SNDR and 96.1dB SFDR with a 19KHz sine wave being fed into the input. The total power consumption is 2.1mW. However, 94.3dB SNDR can be achieved after improving of the comparator`s noise performance, and the FOM value is less than 1pJ/step.