Biography
Enrollment Date: 2010
Graduation Date：2013
Degree：M.S.
Defense Date：2013.05.29
Advisors：Yangdong Deng
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：Research on Parallel Logic Simulation
Abstract:
Hardware Description Language (HDL) is prevalently used in the process of digital Integrated Circuit (IC) design. HDL is used to capture the design of an IC, to verify the correctness of the IC design by simulation and to be synthesized into logic circuits masks for manufacturing. The fast evolvement development of IC manufacturing technology allows extremely complex IC designs, which constantly pose challenges to IC verification methods. Especially, the rapid growth of System-on on-Chips as an example requires simulating hardware and software being verified in a collaborative manner by simulation. As a result, IC verification has become the bottleneck of modern IC design projects. Such a problem has to be resolved with a systematic treatment, among which an essential need is to improve the simulation speed. The complexity and cost of IC design verification becomes an important problem however there is no simple solution. Sophisticated and systematic treatment of the verification problem has attracted a lot of attention. In terms of HDL simulation, it takes a large part of the verification time and thus need to be carefully studied. Both the industry and academic academia world have proposed numerous many different ways to accelerate HDL simulation. Among these, parallel simulation of HDL has been considered as one of the most fundamental solutions. Recent popularization recently the vast adoption of new generations of parallel computing architectures platforms like GP-GPUs and many-core processors shed new light on parallel HDL simulation. The thesis investigates parallel HDL simulation techniques on multi-core CPU platforms. The simulator takes Verilog HDL as its input language and uses CMB algorithm for parallel discrete event simulation. All concurrent design elements in Verilog HDL source files are translated into equivalent Logic Processes (LP), which is the basic unit of concurrent execution of the CMB algorithm. Different LPs concurrently simulate different parts of an IC design and generates signals for dumping. The IC design in Verilog HDL is compiled into a multi-thread program. The program then runs on a multi-processor platform to simulate the IC design. This thesis provides a systematic study on developing and optimizing a multi-core based parallel HDL. We propose a series of essential techniques such as customization of CMB algorithm to parallel HDL simulation, deterministic initialization of simulation, parallel simulation of memory, Logic Process combining, event combining, metrics for circuit concurrency, scheduling of Logic Processes, as well as optimization of queues interconnecting Logic Processes and signal dumping. The proposed simulator is compared with an open source simulator, Icarus Verilog, and a leading commercial simulator ModelSim, in terms of simulation time on a set of real industry designs. On average, the proposed simulator outperforms Icarus Verilog and ModelSim by 6.6 times and 2.4 times, respectively. Experiments also support the effectiveness of functionality, optimization and architecture.