Biography
Enrollment Date: 2010
Graduation Date：2013
Degree：M.S.
Defense Date：2013.05.27
Advisors：Woogeun Rhee
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：PSRR Enhancing Method for Gated Ring Oscillator based Time-to-Digital Converters and its Applications
Abstract:
This paper presents a digital intensive on-chip supply noise monitoring method. By utilizing the gated ring oscillator (GRO) based time-to-digital converter (TDC), the proposed technique effectively collects the multi-phase information of the GRO and provides the resolution 30 times higher than the method using only one GRO output. A prototype supply noise monitor circuit is implemented in 65nm CMOS with an active area of 0.014mm2 and consumes 1.05mW from a 1V supply. This paper discusses a supply noise sensitivity problem of the GRO based TDC in all-digital phase-locked loops (ADPLLs) and presents a power supply rejection ratio (PSRR)-enhancing method. A replica supply noise monitoring circuit is designed to track supply noise and enable feed-forward error cancellation for high PSRR TDC design. A prototype ADPLL with the proposed self-monitored TDC is implemented in 65 nm CMOS to evaluate the supply noise sensitivity of the TDC in the frequency domain. Intermodulation spur generation problem due to noise coupling is also addressed and demonstrated in hardware. The experimental results show that the proposed method effectively suppresses those spurs, achieving the PSRR of 30-to-38 dB.