Biography

Enrollment Date: 2010

Graduation Date：2013

Degree：M.S.

Defense Date：2013.05.28

Advisors：Zhihua Wang

Department：Institute of Microelectronics，Tsinghua University

Title of Dissertation/Thesis：高速串行接口接收端关键技术研究

Abstract:
The high speed SerDes has wide used in many applications, such as communication systems and high performance computing systems. Especially, in today’s computing systems, the bandwidth requirements of chip to chip interconnect has increased significantly. For example, consumer electronic application in PCIE, USB 3.0 and 100GBE protocol in Ethernet are very common in industry product. The data speed of high speed SerDes varies from several Gb/s to 25~28Gb/s. This thesis is focus on the research for receiver technology about equalizer and clock data recover module in sub-10Gb/s high speed wireline transceivers. SerDes channel mode has been analyzed and tested by measure the parameter S11 and S21 of the PCB trace. To solve high frequency attenuation problem, the receiver of SerDes need implant an equalizer. This paper presents a source synchronous receiver design in 65nm CMOS process. The receiver consists of a pre-amplifier which can compensate 6-10 dB channel loss and a half-rate digital CDR based on phase-interpolator. The CDR bandwidth is programmable by using a digital FIR filter. This design uses variable offset amplifier technology to increase sensitivity of the receiver. And a common-mode level shift function is implemented in order to increase the bandwidth of the pre-amplifier. The area for source synchronous receiver without ESD and PAD is 0.045 mm2 and power consumption is 35 mW for 1.2V supply. Then a novel 10Gb/s receiver is proposed in 65nm CMOS process. A decision feedback equalizer and an adaptive equalizer control circuit is implemented for serious channel condition. Behavior simulation of DFE and adaptive algorithm are accomplished by Simulink. In circuit design, 1 tap unrolled DFE and full custom logic circuit for adaptive algorithm are introduced. This chip has been verified in post simulation and tape out.

Publications

Papers：：

[1] Ke Huang,Ziqiang Wang,Xuqiang Zheng,Kunzhi Yu,Chun Zhang,Zhihua Wang, A 5+ 1-lane 3-10 Gbps 3.5 mW/Gb/s source synchronous receiver in 65 nm CMOS technology, Analog Integrated Circuits and Signal Processing, Vol.80, No.3, pp. 519 - 529, 2014.

[2] Kunzhi Yu,Xuqiang Zheng,Ke Huang,Ma Xuan,Ziqiang Wang,Chun Zhang,Zhihua Wang, A 6.4 Gb/s source synchronous receiver core with variable offset equalizer in 65nm CMOS, VLSI-DAT 2013, pp. 1 - 4, 2013.

[3] Kunzhi Yu,Ziqiang Wang,Xuan Ma,Xuqiang Zheng,Chun Zhang,Zhihua Wang, A 6.4 Gb/s data lane design for forwarded clock receiver in 65nm CMOS, MWSCAS 2012, pp. 936 - 939, 2012.

Patents：

[1] Shijie Hu, Ziqiang Wang, Ke Huang, Xuqiang Zheng, Fule Li, Xuan Ma, Kunzhi Yu, Chun Zhang, Zhihua Wang. Clock phase judgment circuit and judgment method in high-speed clock data recovery circuit: China, 201210478209.X[P]. 2015-10-14.