Biography
Enrollment Date: 2010
Graduation Date：2013
Degree：M.S.
Defense Date：2013.05.28
Advisors：Liji Wu
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：Design and Implementation of Embedded EEPROM IP for Automotive Electroinics
Abstract:
Tire Pressure Monitoring Systems (TPMS) is one of the most important automotive active safety assistance systems. TPMS enhances vehicle safety, reduces tire wear and vehicle energy consumption. The data of tire pressure, temperature, acceleration parameters are monitored and displayed in real-time, along with warnings when necessary. Prospects and the market of the passive TPMS are extremely good. Reducing power consumption of the pressure detection chip is one of the key factors to achieve passive TPMS.
EEPROM, a typical nonvolatile semiconductor memory, can be used in SoC as embedded memory. The performance of the embedded EEPROM is closely linked with that of pressure detection chip. EEPROM design for automotive applications is extremely important.
The thesis is mainly about the designing and implementation of embedded EEPROM for the automotive application. Considering the actual application environment and manufacturing process condition, the technical specification of the EEPROM is defined, then, the function and structure of each circuit module are determined. EEPROM circuit consists of storage array, sense amplifier, decoding circuit, address latch, voltage conversion circuit, high voltage generating circuit and digital interface circuit. Special consideration is taken on reducing the power consumption of the circuits, especially in the reading state.
In this paper, the status of TPMS and semiconductor memory is introduced first, espacially the circuits of EEPROM. Then a full-custom design 16K bits automotive EEPROM is proposed. The determination of the technical specifications, the choice of the circuit structure, the simulation results, layout design and packaging are shown. The test program and test platform for the 16K bits EEPROM chip are developed and the test results are analyzed. Test results shown that the periphery circuits is working correctly, at worst case, the averager power consumption of the EEPROM is 1.2mA at read state. Based on the work above, a 64K bits EEPROM is designed and taped out as part of the SoC, The EEPROM is also taped out as a single chip at the same time. The digital interface circuit is automatically placed and routed using EDA software, the rest of the circuit is a full-custom design. Compared to the 16K bits EEPROM, major improvements are increasing the storage capacity, adding a high voltage generating circuits and digital interface circuits. A single 3V power supply and serial data input is achieved, the layout is optimized to improved area utilization. At last, the work is summarized. Focused on low-power and high-efficiency, the sense amplifier, high voltage generation circuit, the voltage conversion circuit and control logic circuit are all optimized.