Biography
Enrollment Date: 2010
Graduation Date：2013
Degree：M.S.
Defense Date：2013.05.29
Advisors：Fule Li
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：The Study on Two-Channel Time-Interleaved Analog-to-Digital Converter
Abstract:
In today's mobile internet era, analog-to-digital converter (ADC) is everywhere: smart phone, iPad, navigator, communication base stations, and so on. With the continuous improvement of the user's experience and the rapid development of IC technology, the ADC with high speed, high resolution, low power has been an important trend. For single channel ADC in a certain process, the sampling rate is difficult to increase, which is determined by the characteristic frequency fT of the process. Even if the sampling rate of single-channel ADC can be very high, the power consumption increases in accordance with the sampling rate as exponential. Time-interleaved ADC can be a good solution to this contradiction, the basic idea is that the multi-channel ADCs sample the same analog signal at different time and output the digital signal by order. There are offset mismatch, gain mismatch, sampling time error among the multi-channels, and these mismatches cause a lot of spurious components in the output's spectrum.
This paper studies the impact of the three mismatches to output spectrum in the time-interleaved ADC. By the modeling and simulation in MATLAB, the calibration algorithm based on interpolation filter and LMS FIR has lower limit to input signal than other algorithms, such as working for low frequency, high frequency, and multi-frequency input signal. That's why this paper selects this algorithm. In order to verify the algorithm, the paper designs PCB and tests the 10-bit two-channel pipelined ADC. The two-channel pipelined ADCs sample the same input analog signal. In order to achieve time interleaving, the inverted clocks which are generated by the inverter on the PCB are the clock signal of the two-channel ADCs. Get the output data by using logic analyzer and verify the algorithm. When the single-channel sampling rate is 51 MS/s, and the input signal frequency is 4.9MHz, before the calibration, SFDR is 16.5dB and ENOB is 2.4-bit, after the calibration, SFDR is 67dB and ENOB is 9-bit. The performance indicators after calibration have reached the level of the single-channel ADC.
Based on SMIC 65nm LL process, this paper designs clock shaping circuit, frequency dividing circuit, LVDS transmitter circuit, output data selecting circuit which are used in 8-bit two-channel time-interleaved ADC. This paper completes the top-level connection of the whole layout. The total area of the chip is 1.1x1.09um2 with the single-channel SAR ADC's area 128x74um2 and LVDS transmitter's area 120x82um2. This paper designs a PCB to test this time-interleaved ADC, tests the chip independently. When the sampling rate of the time-interleaved ADC is 241MS/s, and the input signal frequency is 2.4MHz, before the calibration, SFDR is 30.1dB and ENOB is 4.6-bit, after the calibration, SFDR is 55.6dB and ENOB is 6.3-bit. The performance indicators after calibration have reached the level of the single-channel SAR ADC. The calibration algorithm works very well at other input signal frequency. The digital background calibration algorithm can effectively calibrate the negative impact of these mismatches between the two-channel ADCs.