Biography
Enrollment Date: 2010
Graduation Date：2013
Degree：M.S.
Defense Date：2013.05.29
Advisors：Fule Li
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：Design of a 16bit 1GSPS high speed current-steering Digital-to-Analog converter
Abstract:
In a recent century, human society was brought into unprecedented prosperous by Science and Technology. Integrated Circuit was playing as a decisive role in that process. Digital to Analog converter (DAC) is an important interface circuit block, who bridges the real world and electronic systems. Hence, DAC is widely used and the specification requirement of DAC is getting harder.
There are many specifications to measure a DAC. In applications, DAC focuses on different ones. This paper aimed to design a DAC for high-speed application, such as Base Station, hence, the nonlinearity and SFDR were primarily to be optimized. Resistors, capacitors and MOS are all fundamental elements to figure a DAC. They can be binary weighted or unary weighted. DAC has many implementations, among them; current-steering structure is naturally high-speed and easy to be integrated. So, current-steering structure is quite suitable for this work.
During design, area, power consumption, complexity, and cost should be carefully compromised, and some non-ideal factors should be taken into account: mismatch, finite output impedance, signal asynchronous, input code dependency, etc. This work proposed a 7+4+5 segmented DAC, 7 digits and 4 digits were decoded into thermometer code, 5 digits were remaining as binary. Segment combined both advantages of binary and unary. To eliminating input code dependency, a special quad-switch scheme was introduced with a specific switch driver. The driver limited the voltages swing of switch-control signal for weakening the coupling effect. The thermometer decoder was with two hierarchies. A calibration technique was used for enhancing performance. After circuit simulation and Matlab modeling, the DAC has 16bit resolution with INL 3.3LSB and DNL 0.37LSB. When sample rate is 1GHz, signal frequency is 3.42MHz, the SFDR reached 84.18dB. If signal frequency grew to 101.07MHz, SFDR declined to 78.06dB.