Biography
Enrollment Date: 2010
Graduation Date：2013
Degree：M.S.
Defense Date：2013.05.29
Advisors：Fule Li
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：Study on High-Speed Low-Power Successive Approximation Analog-to-Digital Converter
Abstract:
The continued evolution of theory, technology and process of integrated circuit has caused the trend of greater integration levels and large-scale system on a single-chip (SOC). Meanwhile, with the scaling of MOS feature size and reduction of power supply, the power consumption and area can be reduced effectively. Although the shorter channel length can provide higher-speed, the lower intrinsic gain of MOS transistor may make analog circuit design much harder. Owing to the increasing process-speed of digital circuit also requires much higher speed of analog-to-digital converter (ADC) and digital-to-analog converter (DAC). Successive-approximation analog-to-digital converter (SAR ADC) is efficient in modern process and low-power applications because of not using linearly gain operational amplifiers. How to design and implement a high-speed low-power SAR ADC based on nanometer process, corresponds to the application requirement for the future market.
This paper presents the research on high-speed and low-power SAR ADC from the perspective listed above. The application background of high-speed ADC and the approaches to enhance the speed of ADCs are introduced. The SAR ADC principle and the difficulties involved in nanometer implementation with its solutions are also discussed. The design of a 8-bit 120MS/s SAR ADC IP, which based on SMIC 65nm LL process is provided. The highlights of this design include: ①The design and theoretical calculation method of a DAC network. ②The comparison of full-custom MOM capacitor methods. ③The design of two-stage dynamic comparator and bootstrap switches, using advanced process under a low voltage condition. ④The design and optimization of high-speed and low-power conversion logic circuit. ⑤The considerations and simulation analysis of off-point phenomenon found during the measurement.
In order to improve the SAR ADC conversion speed further, this paper also presents the methods of a 11-bit 160MS/s SAR ADC chip based on SMIC 55nm LL process. It contains 3.5bit Flash ADC and 8 bit SAR ADC by including a redundant code, which is explained to correction error of the highest bit (MSB). The post simulation results of the prototype ADC shows that 10.99-bit ENOB and 82.4dBc SFDR at 5.8MHz input. The performance meets the design requirements.