Biography
Enrollment Date: 2010
Graduation Date：2013
Degree：M.S.
Defense Date：2013.05.29
Advisors：Fule Li
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：Study on High-Performance and Low- Power Pipelined Analog-to-Digital Converter
Abstract:
System-on-chip (SoC) is becoming faster, smaller, more powerful and lower power consumption with the rapid development of the modern CMOS process. Acted as the interface of digital system and analog system, the analog-to-digital converter (ADC) is expected to be high performance and low power.
This thesis presents the research on the design techniques of high-performance and low-power pipelined ADC: Firstly, this thesis reviews and summarizes the various low-power design techniques currently available; and then this thesis proposes a power-efficient circuit structure for the first stage in pipelined ADC. It has the following characteristics: (1) Utilizing the range-scaling technique and the circuit structure of 1-bit redundancy to enlarge the input range and reduce the output swing of inter-stage, so high SNR can be achieved and the low power single-stage opamp can be used with a low supply voltage. (2) Using the sample-and-hold amplifier (SHA)-less technique to remove the front-end SHA to reduce noise and power. (3) Using the opamp sharing and capacitor sharing techniques to reduce the number of opamp and minimize the load capacitance, so the power dissipation is further optimized.
A high-performance and low-power pipelined ADC is implemented with the proposed circuit structure for the first stage. This ADC is fabricated in SMIC 0.13um CMOS process with a 1.2-V supply. Bandgap, the high-speed reference buffer, the low-jitter clock receiver, the LVDS driver and large decouple capacitors are also included in the ADC chip. The total area including pads is 2.1mm×2.1mm with ADC core area of 1.2mm×0.8mm. The simulation results show that the ADC consumes about 68mW with the sampling rate of 200MS/s. The measured results of the ADC chip (2Vp-p input range) show that the ADC consumes about 85mW with the sampling rate of 150MS/s. After foreground digital calibration, the SNR is 71.5dB, the SFDR is 93.3dBc and the ENOB is 11.6 bits for a 2.4MHz input; the SNR is 68.7.5dB, the SFDR is 78.5dBc and the ENOB is 11.0 bits for a 149.9MHz input; the SNR is above 65.0dB when the input frequency is up to 251MHz. The max DNL is +0.48LSB/-0.8LSB and the max INL is +2.6LSB/-2.4LSB. The measured results and the simulation results are some different just because of the layout parasitic. The measure results of the prototype ADC prove that the proposed circuit structure for the first stage is very power-efficient and easy to implement.