Biography
Enrollment Date: 2010
Graduation Date：2013
Degree：M.S.
Defense Date：2013.05.29
Advisors：Baoyong Chi
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：Research on the Digital Baseband Circuit of a Reconfigurable RF Chip for Industry-Specific
Abstract:
This paper presents a digital baseband circuit that is used in Industry-Specific-Network reconfigurable RF chip. This chip uses oversampling technique to improve the SNR (Signal to Noise Ratio), which supports traditional narrowband industry-specific network and LTE cluster communication applications. Simultaneously, it simplify the design difficulty in IF part. The RF chip put the signal processing in the digital side, which is not only meet the design require of reconfigurable, but more approach to the design concept of SDR.
The function of this digital baseband is to down-sampling and down-conversion the output oversampling data of theΣ-△ADC, which transforms the digital signal from low digit occurring at high sampling rate to signal at Nyquist rate and filtered the high-frequency quantization noise that is noise shaping byΣ-△ modulator, and restore the SNR of Σ-△ADC, so that facilitate the demodulation of the baseband chip; In the transmitter, the function of this digital baseband is to up-sampling and up-conversion a good low rate signal of the baseband chip, and then to convert digital signals into analog signals by oversampling DAC, which reduces the design complexity of signal reconstruction filter.
In this paper, I presents a digital baseband circuit, whose varying sampling digital baseband circuit that has a flexible reconfigurable, and it support both low-IF and zero-IF modulation signal, and the data bandwidth support the traditional narrowband Industry-specific applications from 5.6MHz to 2MHz narrowband as well as broadband up to 20MHz.
Variable sampling filter is an important part of the digital baseband circuit, in this paper, I used two five-class associated integrator comb filter (CIC), and adopted increases FIR filter as it’s compensation filter and used for compensating the in-band attenuation, several FIR filter provides an effective channel filtering and interpolation / decimation filtering. Moreover, this special FIR filter that used half-band filter constitutes an interpolation filter array, which meet the up-sampling processing of the high interpolation factor.FIR filter is used multiple times in my design, which will introduce a number of multipliers and adders. In the integrated circuit design, the resource of the multiplier and the adder cause a large consumption. So this paper optimized the FIR filter from two aspects of the structure and coefficient coding method, which narrows the chip area and reduces the power consumption.
The entire circuit through the behavioral modeling and simulation of Matlab, coding by RTL-level, Verilog HDL, and functional simulation and dynamic timing simulation adopt the ModelSim and the NCSim, and the logic synthesis was done by Design Compiler, and finished back-end layout work by Encounter. At last, verifying static timing and formal of chip using Primetime and Formality. After verification, it used TSMC 65nm CMOS mixed-signal process technology to complete the flow sheet. And validated the functions and interfaces of this design by FPGA verification platform during that time.