Biography

Enrollment Date: 2009

Graduation Date：2012

Degree：M.S.

Defense Date：2012.05.25

Advisors：Zhiqiang Gao (Hong Chen Ming Liu)

Department：Institute of Microelectronics，Tsinghua University

Title of Dissertation/Thesis：Research and Development of Flexible Embedded SRAM IP Compiler

Abstract:
Embedded static random access memories (SRAMs) are widely used in system-on-a-chip design. SOC design requires SRAM IP suppliers to provide various SRAMs with different configurations and shapes. It is very difficult for full-custom design to meet these requirements. SRAM IP compiler is widely used in SOC design due to its versatility, reliability and flexibility. Compared with embedded SRAM IP compilers designed by foreign suppliers, domestic SRAM IP compilers only support a specific technology and circuit structure. When memory type, technology or circuit structure changes, compiler needs to be redesigned. This paper presents a flexible compiler design method. The method is suitable for SRAM, ROM and Flash. It is applicable for different technologies and circuit structures. Design complexity is reduced. Firstly, a tool named LayoutBuilder is developped to process layout file. Importing design rules, basic layout templates and algorithm, the tool automatically adds vias, paths and pins to layout and generates resulting GDSII layout file. Secondly, a tool named NetlistBuilder is designed to process SPICE netlist. The tool provides a simple netlist description language and automatically checks ports’ number and alignment and inner and outer floating ports. Thirdly, the dedicated tools LayoutBuilder and NetlistBuilder simplify the design tasks of layout generator and netlist generator. Compiler addressing critical path can be designed conveniently. Simulation and interpolation are used to get timing and power information. The error is below 5%. Eight different compilers, which cover two different technologies (SMIC 65nm low leakage and SMIC 55nm low leakage) and three different circuit structures (high density, low power and high performance), are designed to use this method. All models of 4 different configurations which are generated by SRAM IP compilers have been verified by applying a SOC design process, meanwhile the SOC has been taped out. Six IP cores with different configurations have also been taped out.

Publications

Papers：：

[1] Huamin Cao,Ming Liu,Hong Chen,Xiang Zheng,Cong Wang,Zhihua Wang, Design of High-Speed SRAM Array and Periphery for Compiler, Microelectronics, Vol.43, No.1, 2013.

[2] Cong Wang,Ming Liu,Hong Chen,Xiang Zheng,Huamin Cao,Zhiqiang Gao, Flexible Embedded SRAM IP Compiler Design Methodology Research and Implementation, Microelectronics, Vol.43, No.1, 2013.

[3] Cong Wang,Ming Liu,Hong Chen,Xiang Zheng,Huamin Cao,Zhiqiang Gao, An Embedded SRAM IP Compiler Design Methodology Independent of Technology and Circuit Structure, ICETCE 2012, pp. 246 - 249, 2012.

[4] Xiang Zheng,Ming Liu,Hong Chen,Huamin Cao,Cong Wang,Zhiqiang Gao, A 512 kb SRAM in 65nm CMOS with Divided Bitline and Novel Two-stage Sensing Technique, DDECS 2012, pp. 191 - 192, 2012.

[5] Huamin Cao,Ming Liu,Hong Chen,Xiang Zheng,Cong Wang,Zhihua Wang, Efficient Built-in Self-Repair Strategy for Embedded SRAM with Selectable Redundancy, CECNet 2012, pp. 2565 - 2568, 2012.

Patents：

[1] Huamin Cao, Ming Liu, Hong Chen, Xiang Zheng, Cong Wang, Zhihua Wang, Zhiqiang Gao. A dual-port SRAM unit 6T structure with separate reading and writing: China, 201110282766.X[P]. 2013-12-04.