Biography
Enrollment Date: 2009
Graduation Date：2012
Degree：M.S.
Defense Date：2012.05.24
Advisors：Zhihua Wang Seng-Pan U
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：Research on Timing-skew Calibration Based on Timing-interleaved ADC
Abstract:
A timing-interleaved (TI) analog-to-digital converter (ADC) system is universally used for the purpose of considerable increase of an ADC's sampling rate. Unfortunately, the overall signal-to-distortion-plus-noise ratio (SNDR) performance of TI ADCs is often extraordinarily degraded by timing skew errors caused by the device mismatched in the delay units and clock buffers, as well as the mismatches among clock signal routes. Thus, the timing-skew calibration has been a research hot point these years.
This work presents an 8-bit 800MS/s TI ADC with the technique of background timing-skew calibration, which is proposed to minimize the timing error between channels without any additional calibrating signals. Furthermore, the calibrated output is completely obtained with linear interpolation in the digital domain, and no feedback is needed. In this way, it not only simplifies the circuit design, but also reduces the chip area and power consumption.
The TI ADC consists of two converting successive approximation register (SAR) ADCs and one calibrating SAR ADC. The key features of the 8-bit SAR ADC channel are a resistive Digital-to-Analog Converter (DAC) and a 2-bit per cycle topology. The advantage of using the resistive-string based DAC is that it can provide a large number of reference voltages at same time. Therefore, it can be minimized the chip area greatly compared with the capacitive DAC.
This design is fabricated in advanced 65nm CMOS process, and the ADC occupies 0.72mm×0.33mm = 0.24mm2. The measurement result shows that, from 1V supply, the ADC consumes 3.9mW at 400MSps, resulting in a peak FOM of 65 fJ/conversion-step. The proposed technique can improve the SNDR from 32.0 dB to 45.3 dB at Nyquist input frequency. From 1.2V supply the ADC consumes 9.3mW at 800MSps, resulting in a peak FOM of 88 fJ/conversion-step. Also, the SNDR can be improved from 31.3 dB to 44.3 dB at Nyquist input frequency.