Biography
Enrollment Date: 2009
Graduation Date：2012
Degree：M.S.
Defense Date：2012.05.24
Advisors：Fule Li
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：Study on High-Performance Analog-to-Digital Converter Based on Deep-Sub Micro Technology
Abstract:
In recent years, with the rapid development of IC fabrication process, the integrated level have increased step by step, which underlies the implementation of the concept ‘System on Chip (SoC)’. How to re-design, implement and integrate a module or a chip with the same performances compared with robust applications onto a deep-sub micro (even nanometer) process based SoC, becomes the key technique for the future circuit development.This paper presents the research on high-performance pipelined ADC from the perspective listed above. The application background of high-performance ADC and the approaches to enhance the ADC performances are introduced. The pipelined ADC principle and the difficulties involved in deep-sub micro implementation with its solutions are also discussed. The design of a 65nm 14-bit 250MS/s pipelined ADC IP is provided, which contains the considerations of system, schematic and layout perspective. The highlights of this design include: ①The design of a high-gain, large swing, fast-settling OTA using advanced process under a low voltage condition. ②The design of a high-speed comparator with SHA-eliminating topology application. ③The circuit implementation to coordinate digital background calibration technique. ④The gain-configurable OTA implementation that convenient for digital calibration technique’s verification. ⑤The considerations to obtain an IF-sampling capacity. The post-layout simulation indicates that the performance meets the design specifications.This paper also presents the measurement of a 130nm 12-bit 200MS/s pipelined ADC chip. The method measuring high-speed and high-resolution ADC using FPGA is explored and verified. According to repeatedly adjusting, a rational assisting circuit is refined, proving precious experience on high-performance ADC measurement for the research group. The measurement results reveal that 10.6-bit ENOB and 82.4dBc SFDR at 30MHz input, 10.4-bit ENOB and 77.4dBc SFDR at 120MHz input, under a sampling rate of 200MS/s. The peak DNL and INL are 0.38LSB and 0.84LSB respectively. The chip is capable of operating at a maximum sampling rate of 270MS/s, while the power consumption is 340mW (including on-chip reference buffer and LVDS driver). The chip with QFN package have passed the system verification on the RRH60W feedback channel, Alcatel-Sbell, which indicates that the realized prototype chip is available on certain applications and is proper functioning.