Biography
Enrollment Date: 2009
Graduation Date：2012
Degree：M.S.
Defense Date：2012.05.24
Advisors：Fule Li
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：The Design of Pipelined ADC Based on Digital Calibration Technique
Abstract:
The high-speed high-precision analog-to-digital converters (ADC) are widely used in the field of image processing, information storage and wireless communication. To achieve high speed and high precision, relative to other structures, pipeline architecture ADC has its own advantage: it can take both accuracy and speed into account. With the continuous improvement of the process, the speed limit of the circuit is getting higher and higher, but at the mean time, the process dimension is going smaller and smaller with the supply voltage becoming lower and lower, which makes harder for the opamo to achieve high gain. Therefore, in the deep sub-micron process, the opamp finite gain error performs more and more obviously. Meanwhile, because of the mismatch error of the capacitors, it’s very difficult to achieve high resolution for pipelined ADC based on switched capacitors circuits. Digital calibration techniques are widely used to solve these problems in pipelined ADCs. Digital calibration techniques can convert complex problems of analog circuit accuracy to simple digital signal processing problems and play to the advantage of progress of the process. The existing digital calibration technique is divided into foreground calibration and background calibration.
This paper proposed a digital calibration technique which uses both foreground calibraion and background calirabion. Foreground calibration is simple, but the ADC must be interrupted during the calibration. The background calibration can track the environmental changes, but in general the algorithm is very complex and of slow convergence. The proposed calibration technique combines the foreground calibration and background calibration based on the characteristics of the different error in order to improve the convergence rate. For capacitor mismatch error, because of its relatively stable and will not change with temperature changes, so it can be calibrated by foreground calibration. For the finite gain error of the opamp which is sensitive to environmental changes, the background calibration works. The foreground calibration is done before the ADC is powered on, during which the differential input signal is fixed to zero and then exchange the capacitors connected in to calibrate the capacitors mismatch error. When the ADC is working, the background calibration tracks the changes of the finite gain error with the environment. Due to the foreground calibration process, the initial value of the error has been gotten and because the changes of the environment are generally not too severe, so the background calibration can converge in a very short time. MATLAB behavioral simulation shows that the calibration method could calibrate the linear finite opamp gain error and capacitor mismatch error effectively.
A 14-bit, 250Msps ADC is designed to verify the calibration method. The ADC is consisted with 8 pipelined stages. The former two stages are 3-bit stages with 1 reduntant bit and the following 6 stages are 2.5-bit stages and the last stage is a 3-bit Flash ADC. The whole ADC has a resolution of 17 and the final output is just 14 bits, the 3 reduntant bits are designed to reduce the truncation error brought by the calibration. Simulation results show that the SNDR of the ADC before calibration is 74.93dB, the SFDR is 83.61dB and the enob is about 12.15 bits. After calibration, the ADC is expected to reach 85.62dB SNDR and 103dB SFDR which basically meet 14-bit precision requirements.