Biography
Enrollment Date: 2009
Graduation Date：2012
Degree：M.S.
Defense Date：2012.05.24
Advisors：Fule Li
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：Study on system circuits of 14 bit 250MS/s Pipelined A/D with calibration
Abstract:
The analog to digital convert which is the link between the actual world to the digital system, is absolutely necessary part of the Integrated Circuit system. With the rapid development of the computer, wireless network and digital signal processing, technology, the ADC becomes one of the factors, which restricts those developments. So the ADC with higher speed, higher resolution and lower power are needed for many kinds of places. According to the different use, the ADC’s trends of development are divided to three parts. The first one is high resolution ADC with low speed, which is used in the image, video and video processing technology. The second one is extensively used in Wireless Receiver, which need high speed and the high resolution among 10bit to 14bit or even higher. The last one is used portable devices, which needs low power. This program is based on the second application, as pipelined ADC is both high speed and high resolution, with relatively lower power dissipation.
This paper describes a 14-bit, 250MS/s pipelined A/D converter (ADC) with calibration. To avoid the influence of the aperture error on the ADC’s performance, specially, in the high input signal, the Sampling and Hold circuit is adopted in this program to guarantee input bandwidth. Comprehensive consideration of factors, such as speed, power consumption, noise, 2.5bits/stage has been adopted in quantizer. As the first and second stages are important to the AD’s performance, the calibration is used in these stages. The OTA structure is two stages. The second stage is class AB type, which increased the OTA’s gain with 6dB than the simple Common-source amplifier. The clock jitter is decreased by designing the low noise clock receiver, which makes sure of the high resolution performance. For voltage swing will make bad performance of the ADC, a high speed on chip reference voltage buffer is designed. In the layout, stages are put through the signal alignment direction. This kind of layout will reduce the length of the alignment between the stages; meanwhile the resistance parasitic, which is very important in the high speed analog circuits, is also reduced. The program is implemented in SMIC 0.18μm CMOS process. With the resister and capacitor calibration of the Sample-hold and the first stage, the results are as follow. In the condition of 70MHz sine wave input with a full-range and 250M clock, predicts a SNDR of 76.74dB and 86.10dB SFDR.