Biography
Enrollment Date: 2009
Graduation Date：2012
Degree：M.S.
Defense Date：2012.05.28
Advisors：Chun Zhang
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：Low-Power Design of Digital Baseband Processor for UHF RFID Tag
Abstract:
With the booming of Internet-of-Things (IOT) industry, RFID technology has been widely used in various fields. Compared with low frequency (LF) RFID, ultra high frequency (UHF) RFID has the advantages of high recognition speed, high reliability and great environmental adaptability, which make it become the RFID application highlights in recent years. However，working distance and cost of passive RFID tag are still the bottlenecks which limit its demand. Passive RFID tag’s working distance is determined primarily by the power consumption of the tag, meanwhile, the digital circuits take the greatest proportion of total power consumption. So study of low-power design technology has important practical significance to increase the working distance and meet the application needs.
This thesis studies the main method of low-power digital circuits from the algorithms, structure, logic and physics aspect, and achieves the design of a low-power RFID tag digital baseband processor based on the 18000-6C protocol. The processor is divided into “command receive”, “command processing” and “reply send” three parts, each part consists of several functional sub-modules. This thesis gives a detailed description of the low-power processor’s architecture, the choice of clock frequency and the function, interface signals, low-power implementation and simulation results of each module.
This thesis also describes the design of a digital baseband processor for passive UHF RFID tag based on a simplified protocol. In addition to the traditional low-power design methodology, this design has been improved from the perspective of protocol to further reduce the power consumption of the digital baseband processor. In addition to the low-power digital circuits, this new tag also uses the on-chip antenna (OCA) technology and One-Time Programmable (OTP) memory. After one-time initializational programming and wafer dicing, put a single tag into the 900MHz RF signal area, the tag automatically and continuously sends the identification (ID) information which stored in the OTP memory.
The aforementioned two chips are verified in 0.18µm CMOS technology. For the 18000-6C protocol based RFID tag, a “RFID protocol conformance testing system” is built based on the “Software Defined Radio” technology to test tag’s protocol conformance, confirmed the correctness of the tag’s function. In power consumption aspect, chip measured results show that the 18000-6C tag’s digital baseband processor consumes a power of 2.8µW when the supply voltage is 1V and the input clock frequency is 1.92MHz; When the reader’s transmitting power is 1W, the completed tag can achieve a reading distance of 3m and a writing distance of 1m. On the other hand, the simplified protocol based digital baseband processor consumes a power of 0.8µW under the conditions of 1V supply voltage and 300KHz input clock frequency, meeting the power load requirements of OCA; Measured results show that the completed tag (including OCA, OTP, RF/Analog front-end and the digital baseband processor) can achieve a communication range of 2mm with the reader 1W output power.