Biography
Enrollment Date: 2009
Graduation Date：2012
Degree：M.S.
Defense Date：2012.05.24
Advisors：Shouyi Yin
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：Research on Key Technologies in Short Range Wireless Transceiver
Abstract:
Wireless Multi-mode and Multiband Low Power Transceiver SoC is under intense research in recent years for its broad applications, such as Wireless Sensor Network (WSN), health care and home automation. To meet stringent application requirements such as low cost, limited battery capacity and complex channel environment, both the SoC architecture and optimization techniques need to be carefully designed.
In this paper, we present two digital calibration and compensation techniques to adjust the VCO’s tuning curves in the Σ-Δ fractional-N frequency synthesizer and eliminate the DC offset voltage in the zero intermediate frequency pathway. Fuzzy binary search method is applied to VCO calibration, which guarantees the convergence to the optimal tuning curve without a redundant comparison, at the cost of only a small hardware increase. Experimental results show that with the proposed technique, Σ-Δ fractional-N frequency synthesizer calibration can be completed within 450μs, and lock on the 2.4GHz and 400MHz ISM band with satisfactory phase noise characteristics. Intermediate frequency (IF) gain based DC offset cancellation (DCOC) is designed to remove the DC offset in the zero IF pathway, The DCOC is performed on a 3 stage basis with each stage compensated by a 6 bit DAC to achieve high accuracy and low complexity. To save power, DCOC is conducted only once before a receiving transaction. Experimental results show that DC offset can be cancelled to below 3.5mV for 0 to 60 dB gain, with each calibration process takes less than 1.28ms time.
The digital baseband modulation techniques consist of MSK and FSK with data rates of 100Kbps and 375Kbps respectively. MSK demodulation employs maximum likelihood estimation method and utilizes characteristics of the IEEE802.15.4 spread spectrum code. MSK demodulation hardware combines the sampling point synchronization, preamble detection and payload decoding function in the same data path and finite state machine for simplicity. The FSK uses non-coherent demodulation techniques that can support a modulation index as low as 1. FPGA prototype verification proves that communication can be established between the proposed modulation module and demodulation module in the presence of noise and carrier frequency deviation.
The SoC is fabricated in UMC 0.18-μm 1P6M CMOS technology with 1.8V supply voltage. The overall die area is 4750μm×4100μm, or 19.475mm2. Testing results show that the proposed work is fully suitable for low power, short range wireless communication applications.