Biography
Enrollment Date: 2009
Graduation Date：2012
Degree：M.S.
Defense Date：2012.05.24
Advisors：Chun Zhang
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：Design and Implementation of High Speed Clock Data Recovery Circuit
Abstract:
With the rapid development of computer and communication technology, new applications require higher bandwidth and higher speed, traditional parallel interface is gradually replaced by high speed serial interface. This thesis has discussed critical technology of the clock data recovery (CDR) circuit, which is the main block of receiver system of high speed serial link. This work is chosen from the task “Development and Application of High Speed Serial Interface IP core”, which is supported by National Science and Technology Major Project, “Core Electronic Devices, High-end General Chips and Fundamental Software Product”. The background information of high speed serial interface is introduced. A 6.4Gbps CDR with half-rate clock is presented. The transceiver is based on forward clock SerDes, which has a forward clock lane and five data lanes. This work chooses phase interpolator based CDR from different kinds of CDRs. This paper describes the system analysis and focuses on the linearization model of bang-bang phase detector. Detail description of each block, including sampler, phase interpolator, Demux, phase detector and voting system, controller of phase interpolator and digital filter is also discussed in this paper. The proposed voting system and digital filter can effectively reduce the jitter of high speed CDR. The whole CDR circuit uses the 65nm CMOS technology, and the system function is satisfied with the requirements after post simulation.