Biography
Enrollment Date: 2009
Graduation Date：2012
Degree：M.S.
Defense Date：2012.05.24
Advisors：Chun Zhang
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：Design and Research on Multiphase Delay Locked Loop in High Speed Serial Communication
Abstract:
With the rapid development of the semiconductor technology, the speed of the signal processing in the integrated circuit becomes higher, so the high speed clock generation becomes more important. Delay locked loop is one of the high speed clock generation circuits. With the advantages of low output jitter, small locking time and good stability, the Delay locked loop has become an emerging research area for the high speed serial communication.
This paper describes the background knowledge of the high speed serial communication and phase locked loop. Comparing with phase locked loop, the model and stability of the delay locked loop are analyzed, and then we analyze the phase noise, find the source of the phase noise, and give the method to prevent the phase noise. Finally, we select a delay locked loop which has simple architecture and high performance through comparing different types of delay locked loop. Through careful design and optimization of each block in delay locked loop, we get the delay locked loop circuit which satisfies the specification of the SERDES.
The delay locked loop is fabricated in 65nm technology with power supply 1.2V. The delay locked loop adopts self-biasing technology and jitter attenuation technology to achieve peak to peak jitter 10ps, power consumption 30mW.