Biography
Enrollment Date: 2009
Graduation Date：2012
Degree：M.S.
Defense Date：2012.05.24
Advisors：Baoyong Chi
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：Key Technology Of Power Management In 65nm CMOS
Abstract:
With the development of techniques in design and fabrication of integrated circuits, more functional modules are integrated into a single chip, which is known as the System-on-chip (SOC). Differed to traditional individually functional modules or small-scale systems, a SOC contains both analog and digital sub-systems working at different frequency ranging from DC to multiple gigahertzes, both noisy and sensitive sub-systems handling strong or weak signals simultaneously. Therefore a power management system providing multiple power supplies and voltage/current references is demanding, in which more issues should be considered such as power supply fluctuation, noisy cross talk, and power consumption.
With the improvement of CMOS process and system integrity, more challenges emerge in the design of the power management system. Firstly, as characteristic size is scaling down, the voltage endurance of CMOS devices becomes weaker, and thus the available voltage headroom is greatly limited. This brings design challenges on the basic universal modules such as op-amps with high gain requirement. Secondly, the multiple outputs of the power management system are on different levels and of highly precision. They should be sufficiently isolated in order to prevent noisy cross talk. Thirdly, excellent power supply rejection should be provided to alleviate harms on power fluctuation, which is more significant in mixed-signal SOC cases. Fourthly, low noise requirement must be fulfilled for sensitive internal modules, and fast response in case of loading variation should be satisfied for high speed internal modules. At last, since the SOC is highly integrated, the module amount in the power management system would be large. Therefore, its chip area, belonging bonding pads and external device counts should be limited, and its power consumption should also be concerned.
Based on the significance and challenges of the power management system design above, this work accomplishes the study, design and verification of the bandgap and low drop out regulator (LDO) in the power management system. For each of the two modules, the working principle is studied and base structures are analyzed. Then, a complete design flow is proposed and carried out in 65nm CMOS process. At last, simulation and measurement results are compared to verify the validity of the proposed design approach. Concluded above, there are two main contributions in this work: firstly, two versions of high precision bandgap biasing circuit with multiple outputs and high isolation are accomplished, and their measured performances are provided. Secondly, a fast transient response capacitor-less LDO with low output noise and high Power Supply Rejection Ratio (PSRR) is designed, and its measured performances are derived. Measurement results show that: for the bandgap, its output reference voltage offsets distribute within 6.8% before calibration, and can be improved to below 1.72% after a digital aided on-chip calibration for different samples. For the capacitor-less LDO, the line regulation ratio is 62.65mV/V and the load regulation ratio is 473mV/A.