Biography
Enrollment Date: 2008
Graduation Date：2012
Degree：M.S.
Defense Date：2012.05.24
Advisors：Zhihua Wang，Seng-Pan U
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：Pipelined SAR ADC Based on Digital Calibration and Its Chip Realization
Abstract:
Analog-to-Digital Converters (ADCs) with high performance are crucial in wireless communication systems, digital signal processing and modern instruments.As the downscaling of CMOS technology is becoming increasingly aggressive, the design of traditional pipeline ADCswith high precision requirement has been disposed toward disadvantage positions. Even with digital calibration,the power dissipation of traditional pipeline ADCs is still not optimized enough to accommodate low power consumption tendency.Because the power-friendly quality of SAR ADC has been magnified through downscaling, pipelined SAR ADCs have become a popular research topicfor both high precision and high speed.Still, with the implementation of digital calibration, the power consumption, precision and speed of pipelined SAR ADCs have been pushed into a new level.
The first part of this thesis describes all of the basic knowledge related to the pipelined SAR ADC, which includes the design of sample-and-hold circuits, the introduction of traditional pipeline ADCs, traditional SAR ADCs, three type of digital calibration schemes and traditional pipelined SAR ADCs. The second part of this thesisproposes a new type of 12-bit 120MSPS pipelined SAR ADC implemented with 65nm technology. In this part, all of the featured technologies of the prototype chip are discussed in length and both the design details of schematic level and layout level of thisprototype chip are explained with texts and graphs. The third part of this thesis explained the testing of the prototype chip and illustrated its high precision, high speed and low power consumption testing results, which proved the validity and high performance of the proposed pipelined SAR ADC architecture.