Biography

Enrollment Date: 2008

Graduation Date：2011

Degree：M.S.

Defense Date：2011.05.24

Advisors：Baoyong Chi

Department：Institute of Microelectronics，Tsinghua University

Title of Dissertation/Thesis：Design of Analog Baseband Circuits for Software Define Radio

Abstract:
In this paper we designed a analog baseband circuits for the software defined radio, the architecture of the receiver is zero-IF. And the baseband circuits include a reconfigurable low pass filter, a programmable gain amplifier, the output buffer which aims to drive ADC off chip, also we introduced the direct current offset correction circuits and the cancelling of IQ mismatch. First we design a fifth order low pass Butterworth filter whose cutoff frequency can be tuned from 200 KHz to 20 MHz, the filter are designed with a signal design flow, the circuits are based on Active-RC. Capacitor arrays and resistor arrays are used in the filter to realize a wide range cutoff frequency selected. The amplifier is divided into several of units, and then the power consumption can be reconfigurable by turning on different numbers of amplifier units. This design was taped out under the process of SMIC130nm standard CMOS process. The testing results illustrate that we can get a wide range of power and band wide programmable while the filter acquire a high performance. Then we also design a third order low pass Butterworth filter whose cutoff frequency can be tuned from 5MHz to 50MHz, the circuits are based on Gm-C. Capacitor arrays are used for frequency selected. We introduce a new architecture of transconductor which used a feed forward compensation to improve the linearity. And the design was taped out under the process of SMIC130nm standard CMOS process. Based on the theory which is proved by former works, we improve the analog basebands circuits in the process of TSMC65nm standard CMOS process. The filter is 5MHz to 50MHz low pass Butterworth based on Active-RC, and it can be configured to fifth order or third order. Use a feed forward amplifier to archive higher band wide thus can cut down the power consumption of the filter. The gains of the PGA vary from 0dB to 34dB, which used an open loop circuits. A DC blocking are used inner the circuits, for the output stage we used a DCOC loop to correct the direct currents. An IQ signal cross coupling technology is used to correct the IQ phase mismatch, and vary gain output buffer is introduced here to correct the IQ gain mismatch. In the post layout simulation we proves that the circuits meets all the needs of the design acquires. The current is 6.4mA to 22mA under the supply of 2.5V.

Publications

Papers：：

[1] Xinwang Zhang,Baoyong Chi,Meng Cao,Ling Fu,Zhaokang Xia,Yun Yin,Hongxing Feng,Xing Zhang,Patrick Chiang, Zhihua Wang, A 0.1–4 GHz SDR receiver with reconfigurable 10–100 MHz signal bandwidth in 65 nm CMOS, Analog Integrated Circuits and Signal Processing, Vol.77, No.3, pp. 567 - 582, 2013.

[2] Xinwang Zhang,Yun Yin,Meng Cao,Zhigang Sun,Ling Fu,Zhaokang Xia,Hongxing Feng,Xing Zhang,Baoyong Chi, Ming Xu, Zhihua Wang, A 0.1∼4GHz receiver and 0.1∼6GHz transmitter with reconfigurable 10∼100MHz signal bandwidth in 65nm CMOS, CICC 2012, pp. 1 - 4, 2012.

[3] Ling Fu,Baoyong Chi,Hongxing Feng,Zhihua Wang, A 5M-50M Reconfigurable Gm-C Low-pass Filter in 130nm CMOS for SDR Receivers, ICSICT 2010, pp. 315 - 317, 2010.

Patents：

[1] Baoyong Chi, Xinwang Zhang, Meng Cao, Zhigang Sun, Ling Fu, Yun Yin, Zhaokang Xia, Hongxing Feng, Xing Zhang, Zhihua Wang. A RF front-end circuit of software radio transceiver: China, 201110187783.5[P]. 2013-10-16.