Biography
Enrollment Date: 2008
Graduation Date：2011
Degree：M.S.
Defense Date：2011.05.26
Advisors：Baoyong Chi
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：Research On CMOS Receiver Down Conversion System For Software-Defined Radio Applications
Abstract:
Driven by increasingly sophisticated user demands in 4G era, wireless communication handsets are moving towards multi-standard terminals that could handle various applications. To support multiple different wireless standards, it is highly desirable to implement software-defined-radios (SDRs) where the receiver can be turned over a wide range of frequencies and can support multiple modulation schemes with multiple data rates. High performance, low cost and low power consumption requirements from the next-generation wireless mobile communication applications present the huge challenges for SDR receivers. This work is then focused on the design of CMOS SDR receivers, in particular, on the research of key design techniques about down-conversion system. At the very beginning, direct conversion zero-IF receiver architecture is chosen to realize the overall system, and then specifications for this multimode reconfigurable SDR front-end will be discussed based on LTE communication standard. After that, careful theoretical analysis and simulation is performed on key circuit building blocks including the RF broadband transconductance amplifier (TCA), current driven passive mixer (Mixer) and reconfigurable transimpedance low pass filter (TI-LPF). Finally, implementation of two editions of the SDR down-conversion system (DCS) and corresponding testing work is exhibited. SDRv01_Rx is a receiver front-end chip realized on SMIC 130nm CMOS process. Measured results show that it could provide reconfigurable conversion gain from 35-55dB and signal bandwidth from 3-65MHz with scaling current consumption from 30.5mA to 64.5mA with 1.2V power supply. The measured noise figure (NF) and output third-order intercept point (OIP3) with the maximum gain is 3.5-6dB and higher than 10dBm, respectively, across 0.1-3GHz frequency range. And the die area is 2.4mm2. SDRv02_Rx_DCS is a wideband reconfigurable down-conversion system realized on TSMC 65nm process, whose performance has been significantly improved compared with the previous version. Post-simulation results show that reconfigurable conversion gain from 5-42dB with 1dB step and adjustable signal bandwidth from 5-75MHz with 5MHz step could be obtained. The noise figure (NF) and in-band IIP3 is 7.8-23.7dB and higher than 10dBm, respectively, across 0.1-6GHz frequency band. The scaling current consumption is 2.9-32.1mA with 1.2V power supply and die area is 0.6mm2 for IQ dual channel. During the design and implementation procedure, the reconfigurability of system architecture and the trade-off ability between performance and power consumption has been enhanced compared with traditional design. And a low-power design method is used to extend the signal bandwidth to 100MHz while maintaining a reasonable power consumption level to meet the requirements in 4G era. What’s more, an effective method guaranteeing the stability of multi-loop for the active-RC filter design is proposed.