Biography
Enrollment Date: 2007
Graduation Date：2010
Degree：M.S.
Defense Date：2010.06.10
Advisors：Baoyong Chi
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：Research on Low Power PLL Frequency Synthesizer
Abstract:
As an important part of wireless transceiver, the frequency synthesizer is needed in most of modern transceivers. Its performance has a great effect on the performance of wireless transceivers. Power/area dissipation of the frequency synthesizer is actually large. This thesis presents a low power PLL(phase-locked loop) frequency synthesizer applied in a wireless capsule base station system. In a wireless capsule base station system, low power is an important design target. In a RF PLL frequency synthesizer, VCO(voltage controlled oscillator), prescaler and multi-modulus divider consume almost most of the PLL power due to the high operation frequency. So design keystone of this thesis is placed in the circuit optimization of these three parts. Firstly, an ILFD(injection-locked frequency divider) is used for quaduature LO generation due to its low power dissipation. Compare with other quaduature LO generation circuits, ILFD dissipates lower power at the same phase noise performance. Meanwhile, a wide tuned voltage(0.4～2.9V) is used to expand the frequency band covered by VCO. And varactors are added to ILFD so that the frequency locking range of ILFD can follow the tuned voltage of VCO, to expand the frequency locking range of ILFD equivalently. Consequently a low power, wide locking range ILFD is implemented. Secondly，an adaptive 16/17 dual-modulus frequency divider is used to decrease static current of the ordinary 16/17 dual-modulus frequency divider. In a ordinary 16/17 frequency divider, static current is consumed, but a great deal of that is not necessary. After controlling the static current of non-critical branches, the power consumed by the divider is lowered effectively. The frequency divider could achieve a highest operation frequency of 3GHz. The PLL frequency synthesizer has been implemented in UMC 0.18um CMOS and achieves an output frequency range of 1.9G~2.3GHz. The measured results show that the output quadrature LO signals could achieve phase noise of -88dBc/Hz@100KHz, and the current consumed by VCO and ILFD is only 2.2mA with 1.8V supply voltage (not including buffers), the current consumed by the 16/17 dual-modulus divider is 630uA.