Biography
Enrollment Date: 2007
Graduation Date：2010
Degree：M.S.
Defense Date：2010.06.03
Advisors：Woogeun Rhee
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：A Study and Implementation of Hybrid PLL Technique
Abstract:
As fundamental technique for producing frequency, PLL is very popular for frequency synthesis and clock generation in wireless and wire line applications respectively. IC’s process advancement leads to lower supply voltage and shorter transistor gate length, which difficulties the design of conventional analog PLL. And all digital resolution still faces a lot of challenges, including performance and design cycle. In the thesis, the existing PLL architectures are reviewed and the pros and cons of each one are discussed. Besides a Hybrid PLL technique is presented. The proposed technique is insensitive to leakage current, while it also improves the linearity of phase detection with low hardware cost and smaller area of Chip set. Besides, it lowers the design difficulty of Charge Pump. An integer-N PLL clock generator with the area of loop filter as small as 0.04mm2 and the tuning range of 790MHz to 925MHz in 0.18μm CMOS process. The experimental results show that in-band phase noise is less than -81dBc/Hz, reference spur is less than -52dBc Keywords: PLL Clock Generator Hybrid-PLL