Biography
Enrollment Date: 2007
Graduation Date：2010
Degree：M.S.
Defense Date：2010.06.03
Advisors：Fule Li
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：Design of high-speed current-steering digital-to-analog converter
Abstract:
The recent boom of the telecommunication market has made the interface between digital and analog part one of key building blocks in mix-signal systems. High-speed, high-accuracy digital-to-analog converters (DACs) are demanded in the areas of video, HDTV and wireless communication. For such applications CMOS current-steering DACs are the ideal candidates, since they are inherently fast and can offer high spurious-free dynamic range (SFDR) up till high frequencies. This paper presents a 10-bit 100MS/s and a 12-bit 200MS/s CMOS current-steering DAC for video and communication applications, respectively. The proposed 10-bit DAC adapts segmented architecture, composed of 6 MSBs unary and 4 LSBs binary-weighted cells. Meanwhile, the design of 12-bit is based on the current steering doubly segmented 6+2+4 architecture. To compensate the nonlinearity errors introduce by these systematic gradients, an improved current switching scheme is introduced in this design. The test results prove its efficiency. Low-voltage differential signal (LVDS) receiver is designed for 12-bit DAC especially because of its high sampling rate. Besides the complete presentation of the design and tape-out of the two DAC chips, the thesis also presents the test scheme of the 10-bit DAC and the design of the test board. The test results show that a SFDR up to 71.5dB can be achieved from a full-scale output of 21.6mA and the update rate is 50MS/s with a 2.76MHz input signal. The differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.18 and 0.35 least significant bits (LSB’s), respectively. The full-scale output current can be adjusted by an extra adjustable resistor, range from 2mA to 35mA with 3.3V power supply for analog part, while the digital part of the chip operates at 1.8V. The two DACs are realized in UMC 1P-6M 0.18μm CMOS process. The active area is 0.2 mm2 and 0.56 mm2 respectively. The post-layout simulation shows that the 12-bit DAC can work well to meet the requirements.