Biography
Enrollment Date: 2007
Graduation Date：2010
Degree：M.S.
Defense Date：2010.06.03
Advisors：Fule Li
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：Research and Design of a Pipeline A/D with Digital Background Nonlinear Calibration
Abstract:
With the development of CMOS process, it is difficult for an opamp in MDAC to achieve high gain and high swing range in the same time. Errors associated with finite opamp gains and incomplete settling limit the accuracy of data conversion. By utilizing the development of process and discarding additional highly accurate analog models, digital calibration is superior to other technology, and the superiority is getting more obvious. A 12-bit 50MS/s pipeline A/D prototype with digital background nonlinear calibration is proposed. Under the algorithm, a low-resolution high-speed pipelined core achieves the same accuracy as a high-resolution low-speed reference A/D at its original sampling rate. By dividing the raw output of the pipeline core into different segments addressed by the digital codes defined by the outputs of the first several stages, a code-by-code gain error and offset calibration by using least mean square (LMS) adaptive algorithm is introduced to eliminate the conversion nonlinearity due to circuit non-idealities including nonlinear opamp gain. Prototype utilizes a 3bit stage with open-loop residue amplifier to lower power consumption further. The chip occupies 2.8μm×2.8μm and consumes less than 100mW at 3V power supply in a 0.18μm 1P6M CMOS process. Raw Data from simulation is transferred to Matlab and calibrated by algorithm codes. It is confirmed that the algorithm is effective in significantly improving the conversion accuracy in the presence of various circuit non-idealities.And comparing to existing techniques, it has less limitation on the nonlinear pattern and requires a smaller hardware overhead.