Biography
Enrollment Date: 2007
Graduation Date：2010
Degree：M.S.
Defense Date：2010.06.03
Advisors：Fule Li
Department：Institute of Microelectronics，Tsinghua University
Title of Dissertation/Thesis：The study on 12 bit 100MS/s Pipelined Analog-to-Digital Converter
Abstract:
With the coming of new generation of wireless mobile communication, the digital intermediate frequency receiver in communication systems have become increasingly demanding of speed and precision of the Analog-to-Digital Converter(ADC). Pipelined ADC is the preferred choice because pipelined structure is the best in balancing speed and resolution compared with other structures. At the beginning of the thesis, the research hotpots, fundamental principles and non-ideal effects of pipelined ADC are introduced briefly. Then some optimization strategies and circuit technologies in the design of 12bit 100MS/s pipelined ADC are presented in detail. 1) The advantages and disadvantages of using SHA and removing SHA are discussed. And SHA is adopted to enlarge dynamic range with compromising power dissipation. 2) The first stage adopts 3.5-bit structure to relax the capacitor matching requirements and to improve setting time. 3) Using bootstrapped switch to improve the linearity of sampling switch conduction resistance. 4) Two-stage amplifier using gain-boosting technology is adopted to enlarge DC gain and output swing. 5) In order to generator high-speed low-jitter clock signal to ADC core, the off-chip clock adopts low voltage differential signaling (LVDS) input. 6) Paying special attention to typical nodes to ensure the accuracy of the ADC in layout design. At the end of the thesis, the measurement results of the ADC including two versions are given. Missing code happens in the first version of the ADC. Possible reason causing missing code is proposed and verified using MATLAB behavioral simulation. Then corresponding solution is presented. Based on the first version, the new ADC is taped out with some correction and improvement. With a 15.5MHz input signal, the measured DNL and INL are within -0.22/+0.21 LSB and -0.62/+0.46 LSB respectively at 20MS/s. For the 2.41MHz input, we always have the SFDR over 86dBc and the ENOB over 10.9bit obtained when sampling rate is lower than 100MS/s. For the 15.5MHz input, the ENOB is 10.8bit at 50MS/s, and decreases to 10.5bit at 100MS/s. The ADC is fabricated in 0.18um CMOS process. The silicon area including all pads is 1.95mm×1.80mm, and the power dissipation (including pad drivers) is 112mW.