题目/Title：INVITED PAPER: A 312.5Mbps-32Gbps JESD204C Wireline Transceiver Back-Compatible with JESD204B in 28nm CMOS
作者/Author：
Shijie Li, Ruichang Ma, Mingxing Deng, Jiamin Xue, Baoyong Chi, Haikun Jia
会议/Conference：ICTA 2023
地点/Location：Hefei, China
年份/Issue Date：2023.27-29 Oct.
页码/pages：pp.21-24
摘要/Abstract：
This paper presents a 32Gb/s wireline transceiver that not only supports the JESD204C standard but also maintains back-compatibility with JESD204B with minimal additional circuitry. Additionally, a pattern-filtered phase detector (PFPD) is proposed to circumvent the side effect of ambiguous sampling clock phase caused by loop-unrolled 1st post-cursor tap equalization scheme in the decision-feedback equalization (DFE). Fabricated in 28nm CMOS process, the proposed transceiver demonstrates its ability to operate within a signaling range from 312.5Mbps to 32Gbps, achieving a BER below 10–12 over a 14.9dB channel loss at Nyquist frequency.