题目/Title：一种新型跟踪式逐次逼近模数转换器
                        A A New Tracking SAR ADC

作者/Author：于宝亮,冯海刚
                        Baoliang Yu,Haigang Feng

期刊/Journal：微电子学与计算机 Microelectronics & Computer

年份/Issue Date：2018.Jan.

卷（期）及页码/Volume（No.）&pages：Vol.35, No.1, pp. 124-127+132

摘要/Abstract：
为了降低功耗和复杂度，采用复用量化器结构，而不需要传统结构中的减法和数模转换器模 块（DAC） ，实现一低功耗简单的跟踪式模数转换器。量化器采用 8-bit 电容单调式切换的逐次逼近模 数转换器（SAR ADC） 。另外为了进一步提高效率，SAR ADC 中的比较器采用时间域比较器实现。经过 在 90nm CMOS 工艺下仿真验证，设计的 ADC 采样速度 16MHz，8 倍过采样率（OSR） 。经过数字滤波处理， 输入信号频率为 227KHz 时，可以实现 59.6dB 的信噪失真比（SNDR） ，功耗
This paper presents a tracking analog-to-digital converter (ADC). By reusing the quantizer, the tracking ADC no long needs subtraction and digital-to-analog (DAC) module that the conventional structure needs. This technique could decrease the power consumption and the chip area. The quantizer adopts 8-bit monotonic switching scheme successive-approximation-register (SAR) ADC. In addition, to further increase efficiency, a time domain comparator is used to replace the analog domain comparator. This ADC is simulated in a 90nm CMOS technique. It works with 16MHz sampling rate, 8 over sampling rate (OSR). It achieves 59.6dB SNDR for an input signal around 227KHz with the help of a simple digital low pass filter. Counting in the filter, it consumes 28.5uW power under 1-Vsupply. The figure-of-merit (FOM) is 18.4fJ/STEP. In addition, such topology bring us the advantage of easy design migration among technology nodes for seeking greater efficiency improvement.