题目/Title：Soft-Edge error-detecting flip-flop for lowering error-correction-rate under ultra-low voltage

作者/Author：雷顺,李翔宇,刘亚斐
                        Shun Lei,Xiangyu Li,Yafei Liu

会议/Conference：EDSSC 2017

地点/Location：Hsinchu, Taiwan

年份/Issue Date：2017.18-20 Oct.

页码/pages：pp. 1 - 2

摘要/Abstract：
This paper presents a Soft-Edge Error-Detecting Flip-Flop (SEED FF), which can be used in Ultra-Low-Voltage (ULV) digital circuits to address timing variation problems with a lower timing error correction rate. The master latch’s clock edge of a timing error detecting flip-flop is delayed so that it has not only the timing error detection capability but also a narrow transparency window. HSPICE simulations show that the performance of S386 of ISCAS’89 using SEED FF is improved by 31.36% at 0.35V compared with the traditional error detecting flip-flops.